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US 4,119,916 AGranted
Programmable charge coupled device timing system
AssigneeThe United States of America as represented by the Secretary of the Navy
InventorHerbert Berke
Life of this patent
Estimating the term…
Abstract
A universal timing circuit for enabling numerous different types of charge oupled devices is disclosed which permits the operation thereof to be established over a wide range of counted and programmed clock input frequencies, thereby facilitating experimentation in faster scanning techniques, such as, for example, those which might be required when charge coupled image sensing devices are used as substitutes for vidicon tubes in various and sundry television systems.
Claims17
Means for generating a plurality of timing signals, comprising in combination:
- a clock signal generator;
- a first flipflop having an input, a Q output, and a Q output, with the input thereof connected to the output of said clock signal generator;
- a second flipflop having a set input, a reset input, a Q output, and a Q output, with the set input thereof connected to the Q output of said first flipflop;
- counter means having a clock input, a preset input, and an output, with the clock input thereof connected to the output of said clock signal generator;
- another flipflop having a set input, a reset input, a Q output, and a Q output, with the set input thereof connected to the output of said counter means, with the reset input thereof connected to the preset input of said counter means, and with the Q output thereof connected to the reset input of said second flipflop;
- and
- delay means effectively connected between the Q output of said another flipflop and the preset input of the aforesaid counter means for timely supplying a predetermined delayed signal thereto and to the reset input of said another flipflop.
4 more elements
A charge coupled device signal generator, comprising in combination:
- means for generating a fundamental frequency first signals;
- means connected to the output of said fundamental frequency first signal generating means for simultaneously generating a second signal having a frequency that is one-half that of said first signal, and third and fourth frequency signals, the third of which is one hundred and eighty degrees out of phase with the fourth thereof, with the polarity of the fourth signal thereof in concurrence with that of the aforesaid second signal;
- means connected to one of the outputs of said last mentioned means for simultaneously generating a fifth signal that has half the frequency of the aforesaid third signal and a sixth signal that has the same frequency as said fifth signal and is 180.degree. out of phase therewith in response to a seventh signal;
- means effectively connected between an output of said third signal producing means and an input of said fifth and sixth signal producing means for timely supplying said seventh signal thereto and for generating an eighth output signal that has been delayed a first predetermined time period with respect to the beginning of the aforesaid fifth signal;
- and
- means connected to an output of said last mentioned means for generating a ninth signal that has been delayed a second predetermined time period with respect to the beginning of the aforesaid fifth signal that is less than the delay of said eighth output signal.
3 more elements
A signal generating system, comprising in combination:
- a clock signal generator;
- a first flipflop having a trigger input and a pair of outputs, with the trigger input thereof connected to the output of said clock signal generator;
- a second flipflop having a set input, a reset input, and a pair of outputs, with the set input thereof connected to one of the outputs of said first flipflop;
- a control gate having a clock input, a control input, and an output, with the clock input thereof connected to the output of said clock signal generator, and with the control input thereof connected to the other output of said first flipflop;
- counter means having a clock input, a preset input, and an output, with the clock input thereof connected to said one of the outputs of said first flipflop;
- a third flipflop having a set input, a reset input, and a pair of outputs, with the set input thereof connected to the output of the aforesaid counter means, and with one of the outputs thereof connected to the reset input of said second flipflop;
- a first one-shot multivibrator having an input and a pair of outputs, with the input thereof connected to the other output of said third flipflop;
- a second one-shot multivibrator having an input and an output, with the input thereof connected to one of the outputs of said first one-shot multivibrator;
- a third one-shot multivibrator having an input and a pair of outputs, with the input thereof connected to the output of said second one-shot multivibrator;
- and
- a delay means connected between one of the outputs of said third one-shot multivibrator, the reset input of said third flipflop, and the preset input of the aforesaid counter means for timely delaying a preset signal thereto.
8 more elements
A charge coupled device signal generator, comprising in combination:
- means for generating a fundamental frequency first signal;
- means connected to the output of said fundamental frequency first signal generating means for simultaneously generating a second signal having a frequency that is one-half that of said first signal, and third and fourth frequency signals, the third signal of which is 180.degree. out of phase with the fourth signal thereof, with the polarity of the fourth signal thereof being in concurrence with that of the aforesaid second signal;
- means connected to one of the outputs of said last mentioned means for simultaneously generating a fifth signal that is one-half of the frequency of the aforesaid third signal and a sixth signal that has the same frequency as said fifth signal and is 180.degree. out of phase therewith in response to a seventh signal;
- means effectively connected between an output of said third signal producing means and an input of said fifth and sixth signal producing means for timely supplying said seventh signal thereto and for producing eighth and ninth signals that have been respectively delayed first and second predetermined time periods with respect to the beginning of the aforesaid fifth signal, said means including counter means having a clock input and a preset input, with the clock input thereof connected to the output of said third signal producing means;
- a flipflop having a set input, a reset input, a Q output, and a Q output, with the set input thereof connected to the output of said counter means, and with the Q output thereof connected to said input of the aforesaid fifth and sixth signal producing means;
- and a delay means having an input and an output, with the input thereof connected to the Q output of said flipflop and with the output thereof connected to the preset input of said counter means and the reset of the aforesaid flipflop.
3 more elements
Dependencies are inferred from the claim text.