Microprogram memory bank addressing system

In a data processing system having a plurality of registers for storing electronic signals and a read only memory (ROM) system, said ROM system having at least one read only memory (ROM) having a plurality of banks of memory, each bank for storing a plurality of microprograms, each microprogram comprised of a plurality of microwords, each microword comprised of a plurality of bits, any of said microwords, stored in said ROM, being addressed by a predetermined number of bits stored in a ROM address register (RSAR) coupled to said ROM, said RSAR being one of said plurality of registers, said ROM system further comprised of a ROM local register (RSLR) also coupled to said ROM for storing any of said microwords read from said ROM during a current cycle, any of said microwords addressed by said predetermined number of bits stored in said RSAR during a previous cycle, an apparatus for increasing the capacity and speed of access of said ROM system comprising:

• (a) first means, in said ROM system, for storing first coded signals for addressing any one of said plurality of registers;
• (b) second means, in said first means, for storing second coded signals of a predetermined first constant indicating a predetermined one of said plurality of registers, said predetermined one of said plurality of registers being said RSAR;
• (c) third means, in said first means, for storing third coded signals of a predetermined second constant indicating a predetermined one of said plurality of banks;
• and
• (d) fourth means, coupled to said RSLR and to said RSAR and to said third means for transferring said third coded signals to said RSAR during said current cycle, whereby said predetermined one of said plurality of banks can be selected for reading in a next cycle by executing a predetermined one of said microwords during said current cycle.