US 4,116,720 A · Method of making a V-MOS field effect transistor for a dynamic memory cell having improved capacitance

Abstract

This disclosure relates to a method of making a V-MOS field effect transistor which does not require the extra steps of epitaxial growth in order to form the source area of the transistor. The formation of the source area is achieved by masking the silicon substrate, opening an aperture in the mask and then etching the silicon substrate in such a manner as to undercut the mask so that the mask provides a shield to subsequent ion implanting of the source area. Both P and N type dopants can be separately implanted with different energy levels so as to form an enhanced PN junction capacitance for the device. Such a field effect transistor can be achieved without the formation of a graded dopant concentration in the channel between the source and drain areas of the transistor and is provided with enhanced source capacitance.

Claims10

Dependent claims

A method of forming a field effect transistor comprising the steps of:

forming a masking layer over the surface of a crystalline substrate;
opening an aperture in said masking layer to expose said surface of said substrate;
applying an etchant to said exposed substrate to form a V-shaped recess in said substrate so that the recess is wider at said substrate surface than the aperture in said masking layer;
and
accelerating ions through said aperture in said masking layer for implantation in said substrate around the lower portion of said V-shaped recess.

2 more elements

Dependencies are inferred from the claim text.

Method of making a V-MOS field effect transistor for a dynamic memory cell having improved capacitance

Life of this patent

Method of making a V-MOS field effect transistor for a dynamic memory cell having improved capacitance

Life of this patent

Abstract

Claims10