Conditional bypass of error correction for dual memory access time selection

A method of conditionally bypassing the error correction circuitry of an error correcting system, comprising:

• coupling a memory address to a first memory;
• reading out the uncorrected read bits that are stored at the addressed addressable location in said first memory;
• coupling said memory address to a second memory;
• determining if said memory address is stored in said second memory;
• generating a Match signal if said memory address is stored in said second memory or, alternatively, generating a Match signal if said memory address is not stored in said second memory;
• coupling said uncorrected read bits to error correction circuitry;
• generating corrected read bits from said uncorrected read bits;
• coupling said uncorrected read bits to gating means;
• coupling said corrected read bits to said gating means;
• gating said uncorrected read bits from said gating means in response to said Match signal at a relatively fast memory access time or, alternatively, gating said corrected read bits from said gating means in response to said Match signal at a relatively slow memory access time.

A method of conditionally bypassing the error correction circuitry of an error correcting memory system, comprising:

• coupling a multibit memory address to an addressable memory;
• reading out the uncorrected read bits that are stored at the addressed addressable location in said addressable memory;
• coupling said multibit memory address to a content addressable memory;
• determining if said multibit memory address is stored in said content addressable memory;
• generating a Match signal if said multibit memory address is stored in said content addressable memory or, alternatively, generating a Match signal if said multibit memory address is not stored in said content addressable memory;
• coupling said uncorrected read bits to error correction circuitry;
• generating corrected read bits from said uncorrected read bits;
• coupling said uncorrected read bits to interface registers;
• coupling said corrected read bits to said interface registers;
• gating said uncorrected read bits from said interface registers in response to said Match signal at a relatively fast memory access time or, alternatively, gating said corrected read bits from said interface registers in response to said Match signal at a relatively slow memory access time.