US 4,107,549 A · Ternary logic circuits with CMOS integrated circuits

Abstract

Ternary storage elements are realized using ternary operators and fundamental circuits, designed to make practical use of CMOS (or COS/MOS) integrated circuits. Word-organized and trit-organized memory cells are designed for the construction of a ternary random-access-memory array (TRAM). Several flip-flops (tri-flops) are constructed and described in detail, including a PZN (set positive, set zero and set negative), a clocked PZN, a D-type and a T-type. Ternary shift registers and ring counters are formed by means of these tri-flops. A master-slave T-type tri-flop is used for the construction of a ternary up counter which is able to count from 0 to 3.sup.n using the normal ternary code or from --(3.sup.n -1)/2 to +(3.sup.n -1)/2 when the signed-ternary code is employed. With a little modification, a ternary down counter may also be constructed. A divide-by-M ternary counter which can be programmed is described. A ternary decoder and encoder are presented, which are the elements of a complete ternary read-only-memory (TROM). A modified ternary inverter (MTI) is taken as a unit cell of a ternary memory matrix.

Claims12

Dependent claims

A three-valued logic operator having discrete positive, zero and negative output signal values for discrete negative, zero and positive input signal values, respectively, comprising:

an input terminal connected to the gates of a pair o complementary p-type and n-type metal oxide semiconductor devices, at least the sources of which are each respectively connected to equal and opposite power supplies of positive and negative value, respectively, and the drains of which are each connected to one of a pair of equal-valued resistors;
said pair of equal-valued resistors having a common connection to each other at the ends of each opposite the drains of the respective p-type and n-type metal oxide semiconductor devices;
and
a first output terminal connected to the common connection of said pair of equal-valued resistors;
whereby for each of said positive and negative input signal values, only one of said semiconductor devices is conductive to produce the respective output signal value;
and when the input signal value is at the zero level, both of said semiconductor devices are conductive.

3 more elements

A three-valued logic operator having two-entry, three-valued input and having ternary NOR output, whereby the input and output signal values have discrete positive, zero and negative levels, comprising:

two pairs of complementary p-type and n-type metal oxide semiconductor devices, where the first and second p-type devices are connected in series and the first and second n-type devices are connected in parallel;
a pair of input terminals, the first of which is connected to the gate of said first p-type metal oxide semiconductor device and to the gate of said second n-type metal oxide semiconductor device, the second of said input terminals being connected to the gate of said second p-type metal oxide semiconductor device and to the gate of said first n-type metal oxide semiconductor device;
the source of said first p-type metal oxide semiconductor device being connected to a positive power supply, the source of said second p-type metal oxide semiconductor device being connected in series with the drain of said first p-type metal oxide semiconductor device;
the substrates of said p-type metal oxide semiconductor devices being connected to said positive power supply;
the source and substrate of each of said n-type metal oxide semiconductor devices being connected to a negative power supply;
the drain of said second p-type metal oxide semiconductor device being connected to the first of a pair of equal-valued resistors, and the drain of each of said n-type metal oxide semiconductor devices being connected to the second of said pair of equal-valued resistors, there being a common connection of said equal-valued resistors to each other and to an output terminal.

3 more elements

A three-valued logic operator having two-entry, three-valued input and having ternary NAND ouput, whereby the input and output signal values have discrete positive, zero and negative levels, comprising:

two pairs of complementary p-type and n-type metal oxide semiconductor devices, where the first and second p-type devices are connected in parallel and the first and second n-type devices are connected in series;
a pair of input terminals, the first of which is connected to the gate of the first n-type metal oxide semiconductor device and to the gate of the first p-type metal oxide semiconductor device, the second of said input terminals being connected to the gate of said second n-type metal oxide semiconductor device and to the gate of said second p-type metal oxide semiconductor device;
the source of said second n-type metal oxide semiconductor device being connected to a negative power supply, and the source of said first n-type metal oxide semiconductor device being connected in series with the drain of said second n-type metal oxide semiconductor device;
the substrates of said n-type metal oxide semiconductor devices being connected to said negative DC power supply;
the source and substrate of each of said p-type metal oxide semiconductor devices being connected to a positive power supply;
the drains of each of said first and second p-type metal oxide semiconductor devices being connected to the first of a pair of equal-valued resistors, and the drain of said first n-type metal oxide semiconductor device being connected to the second of said pair of equal-valued resistors, there being a common connection of said equal-valued resistors to each other and to an output terminal.

3 more elements

Dependencies are inferred from the claim text.

Ternary logic circuits with CMOS integrated circuits

Life of this patent

Ternary logic circuits with CMOS integrated circuits

Life of this patent

Abstract

Claims12