Power-on reset semiconductor integrated circuit

In a semiconductor integrated circuit chip having digital circuit means formed of MOS transistors constructed and arranged on a substrate to define a predetermined parasitic capacitance, the improvement comprising a voltage supply means including a reference terminal and a supply voltage terminal for selectively applying to said digital circuit means a supply voltage for operating said digital circuit means at said supply voltage, and reset circuit means disposed intermediate said supply voltage terminal and said reference terminal, said reset circuit means including at least first and second complementary coupled opposite polarity MOS transistor means coupled to define an output terminal having said predetermined parasitic capacitance thereat, said first transistor means being further coupled to said reference terminal and said second transistor means being further coupled to said supply voltage terminal so that said first transistor means is turned ON and defines a predetermined resistance between said reference terminal and said output terminal when said supply voltage is initially applied to said reset circuit means and defines in series with at least said parasitic capacitance between said output terminal and said supply voltage terminal an RC constant so that a reset signal is applied at said output terminal to said digital circuit means a predetermined interval of time after said supply voltage is initially applied to said reset circuit means and digital circuit means.