21/2D core memory

A core memory comprising:

• a plurality of magnetic memory cores which are switchable between two stable states of magnetization in response to the coincidence of partial select currents inductively coupled thereto, the cores including first, second, third and fourth cores;
• a plurality of conductors arranged to enable the selective switching of each core in response to partial select currents in the conductors, the plurality of conductors including a first conductor inductively coupling current therein to the first and third cores, a second conductor inductively coupling current therein to the second and fourth cores, a third conductor inductively coupling current therein to the first and second cores, and a fourth conductor inductively coupling current therein to the third and fourth cores;
• and
• current control circuitry coupled to provide partial select currents in the plurality of conductors to selectively switch the cores, the current control circuitry being operable to continuously maintain partial select currents in the first and second conductors during a memory cycle while providing partial select currents in the third and fourth conductors, the inductive coupling of the cores by the currents in the first, second, third and fourth currents being such that the currents in the third and fourth conductors are each coincident with a different one of the currents in the first and second conductors and anticoincident with the other.

A core memory comprising:

• a plurality of groups of magnetic memory cores which are switchable between two stable states of magnetization;
• a plurality of Y conductors, each inductively coupled to a mutually exclusive Y subgroup of cores from each group;
• a plurality of X conductors for each group of cores, each X conductor being inductively coupled to a mutually exclusive X subgroup of cores from one group, with each X subgroup including one core from each Y subgroup of cores of said one group;
• and
• control circuitry coupled to execute a memory cycle during which a multibit data word is read from or written into a multiple core, memory word location a single address, said memory cycle being executed in a plurality of time sequential memory subcycles with a different portion of the multibit data word being read from or written into said defined memory word location during each memory subcycle.

A core memory comprising;

• at least four groups of magnetic memory cores which are switchable between two stable states of magnetization;
• a plurality of Y conductors, each inductively coupled to a mutually exclusive Y subgroup of cores from each group;
• a plurality of X conductors for each group of cores, each X conductor being inductively coupled to a mutally exclusive X subgroup of cores from one group, with each X subgroup of cores including one core from each Y subgroup of cores of said one, the X conductors for each group of cores each having a drive end and an opposite sink end with the drive ends coupled in X drive subgroups having the drive ends of all X conductors within each X drive subgroup coupled in common and with the sink ends coupled in X sink subgroups having the sink ends of all X conductors within each X sink subgroup coupled in common and with the X drive and sink subgroups arranged such that each X drive subgroup includes one X conductor from each X sink subgroup and each X sink subgroup includes one X conductor from each X drive subgroup;
• and
• control circuitry coupled to execute a memory cycle during which a multibit data word is read from or written into a multiple core, memory word location defined by address information, said memory cycle being executed in a plurality of time sequential memory subcycles with a different portion of the multibit data word being read from or written into said defined memory word location during each memory subcycle, the control circuitry including (1) X drive decoder circuitry coupled to enable the passage of a partial select current in a commanded direction through the X conductors of a defined X drive subgroup from each group within a commanded one of two drive super groups each of which includes two different groups, the X drive subgroup being defined by an X drive portion of the address information, (2) X sink decoder circuitry coupled to enable the passage of a partial select current of a commanded direction through the X conductors of a defined sink drive subgroup from each group within a commanded one of two X sink super groups each of which includes a different group from each X drive super group, the sink drive subgroup being defined by an X sink portion of the address information, and (3) sequence and timing circuitry coupled to command a direction of current through the X drive decoder circuitry and X sink decoder circuitry, command selection of one of two X drive super groups and command selection of one of two X sink super groups.

A core memory comprising:

• at least two arrays of memory cores which are switchable between two stable states of magnetization, each array containing a plurality of orthogonal rows and columns of cores permitting unique identification of a core within an array by a row position and a column position;
• a plurality of Y conductors, each Y conductor being inductively coupled to all of the cores in one column of cores in each array;
• a plurality of X conductors, each X conductor being inductively coupled to one row of cores in one array, each array having a plurality of rows of cores inductively coupled by X conductors;
• Y decoder circuitry coupled to select at least one Y conductor to the exclusion of other Y conductors in response to memory address information;
• X decoder circuitry coupled to select exactly one X conductor from each array in response to memory address information;
• current control circuitry coupled to operate during a memory read cycle to continuously pass a partial select switching current through the at least one Y conductor selected by the Y decoder circuitry while passing partial select switching currents through the X conductors selected by the X decoder circuitry, the partial select currents through each X conductor being initiated at a different time;
• and
• sense amplifier circuitry coupled to sense core switching signals appearing on the Y conductors during a memory read cycle and sequentially indicate the presence or absence of a core switching signal following each initiation of a partial select current through each different X conductor.

A core memory comprising:

• a plurality of multibit shift registers, each having a shift input, a plurality of parallel inputs coupled to receive data in parallel and a plurality of parallel outputs coupled to provide data in parallel;
• each shift register being coupled to shift therein a plurality of data signals received sequentially from a sense amplifier during a memory read operation;
• a plurality of multiplexers, each being coupled to receive data from the parallel outputs of a shift register and to output a selectable two data signals in response thereto;
• a plurality of Y current sources coupled to provide a pair of Y read currents during a memory read operation and a pair of opposite polarity Y write currents during a memory write operation;
• a plurality of sets of Y drive decoder switches, each being arranged to couple a pair of Y currents from a current source to an address selected pair of Y drive switch conductors respectively, and each including a pair of Y series switches, each Y series switch being coupled to selectively unhibit a different write current in response to a different one of the data signals from a multiplexer;
• a plurality of sense amplifiers, each being coupled to sense core switching voltage signals superimposed upon a pair of Y read currents at a current source therefore and communicate a sequence of data signals indicative of sensed core switching voltage signals to a shift input of a shift register during a memory read operation;
• a plurality of Y decoder diode matrices, each coupling pairs of drive switch conductors from a set of Y drive decoder switches to a plurality of pairs of Y conductor pairs at drive ends thereof;
• a plurality of frames of bistable magnetic memory cores, each frame including rows and columns of cores inductively coupled by X conductors having opposite drive and sink ends along the rows and Y conductor pairs having opposite drive and sink ends along the columns with each Y conductor inductively coupling a column of cores from each frame, each pair of cores inductively coupled by an X conductor and a pair of Y conductors being inductively coupled with first and opposite polarities;
• a set of Y sink switches arranged to couple the sink ends of a plurality of pairs of address selected Y conductors to a voltage source to enable the passage through all of the core frames of one pair of Y currents for each set of Y drive decoder switches;
• a pair of X current sources providing opposite polarity partial select X currents;
• a set of X drive decoder switches arranged to couple the X current sources to address selected X drive switch conductors;
• an X decoder diode matrix for each frame, each matrix coupling drive ends of X conductors to X drive switch conductors with a plurality of X conductor drive ends being coupled to each X drive switch conductor;
• first and second sets of X sink switches each having a plurality of X sink conductors, each coupled to a plurality of X conductors such that selection of the X drive conductor and an X sink conductor uniquely selects an X conductor and each arranged to couple an address selected X sink conductor to a series switch;
• first and second pairs of series switches coupling selected X sink conductors of the first and second sets of X sink switches respectively to opposite polarity voltage sources;
• and
• timing and control circuitry coupled to control the switches of the core memory to provide during a read operation a pair of continuous partial select Y read currents for each set of Y drive decoder switches and a partial select X read current for each frame, the X read currents being initiated sequentially with each next X read current being initiated after a switching of a core has been sensed for any immediately preceding X read current, and to provide during a write operation the enabling of a pair of partial select Y write currents for each set of Y drive decoder switches and a partial select X write current for each frame with partial select X write currents for pairs of frames being provided in sequence and with the pairs of Y series switches being responsive to different data from the multiplexers while partial select write current passes through each different pair of frames.

A core memory sense amplifier circuit comprising:

• a differential amplifier having inputs coupled to sense a differential voltage across a pair of conductors and an output coupled to generate an output signal indicative of the differential voltage;
• a first capacitor having a first terminal coupled to the output signal of the differential amplifier and an opposite second terminal;
• a second capacitor having a first terminal coupled to a constant voltage source and an opposite second terminal;
• a circuit coupled to equalize the voltages on the second terminals of the first and second capacitors before core switching signals are to be sensed and to present a high impedance to the second terminals as core switching signals are sensed;
• and
• a comparator coupled to indicate the occurance of a voltage differential across the second terminals greater than a threshold voltage.

A core memory comprising:

• a plurality of magnetic memory cores which are switchable between two stable states of magnetization in response to the coincidence of partial select currents inductively coupled thereto, the cores including first, second, third and fourth cores;
• a plurality of conductors arrnged to enable the selective switching of each core in response to partial select currents in the conductors, the plurality of conductors including a first conductor inductively coupling current therein to the first and third cores, a second conductor inductively coupling current therein to the second and fourth cores, a third conductor inductively coupling current therein to the first and second cores, and a fourth conductor inductively coupling current therein to the third and fourth cores;
• and
• current control circuitry coupled to provide partial select currents in the plurality of conductors to selectively switch the cores, the current control circuitry being operable during each cycle of the memory to continuously maintain partial select currents in the first and second conductors while sequentially providing partial select currents in the third and fourth conductors, the inductive coupling of the cores by the currents in the first, second, third and fourth currents being such that the currents in the third and fourth conductors are each coincident with a different one of the currents in the first and second conductors and anticoincident with the other, the third and fourth currents each being coincident with a different one of the first and second currents.

A core memory comprising:

• a plurality of groups of magnetic memory cores which are switchable between two stable states of magnetization;
• a plurality of Y conductors, each inductively coupled to a mutually exclusive Y subgroup of cores from each group, said Y conductors being grouped into pairs of Y conductors across which core switching signals are differentially sensed;
• a plurality of X conductors for each group of cores, each X conductor being inductively coupled to a mutually exclusive X subgroup of cores from one group, with each X subgroup including one core from each Y subgroup of cores of said one group;
• and
• control circuitry coupled to execute a memory cycle during which a multibit data word is read from or written into a multiple core, memory word location defined by address information, said memory cycle being executed in a plurality of time sequential memory subcycles with a different portion of the multibit data word being read from or written into said defined memory word location during each memory subcycle, a plurality of said cores of a memory word being inductively coupled by a pair of Y conductors with each core of said plurality being in a different group with half of said plurality of cores being inductively coupled by one of the pair of Y conductors and the other half being inductively coupled by the other of the pair of Y conductors.

A core memory comprising:

• at least one pair of groups of magnetic memory cores which are switchable between two stable states of magnetization;
• a plurality of Y conductor pairs, each Y conductor inductively coupled to a mutually exclusive Y subgroup of cores from each group;
• a plurality of X conductors for each group of cores, each X conductor being inductively coupled to a mutally exclusive X subgroup of cores from one group, with each X subgroup including one core from each Y subgroup of cores of said one group, each X conductor inductively coupling the cores of pairs of Y subgroups corresponding to Y conductor pairs in first and opposite orientations;
• and
• control circuitry coupled to execute a memory cycle during which a multibit data word is read from or written into a multiple core, memory word location defined by address information, said memory cycle being executed in a plurality of time sequential memory subcycles with a different portion of the multibit data word being read from or written into said defined memory word location during each memory subcycle with each pair of Y conductors having one Y conductor inductively coupling a core for a memory word in one group of a pair of groups also having the Y conductor opposite the one Y conductor of the pair of Y conductors inductively coupling a core of the memory word in the group opposite the one group in the pair of groups of memory cores.