Protection circuit to minimize the effects of power line interruptions on the contents of a volatile electronic memory
AssigneeRockwell International Corporation
InventorJohn W. Footh
Life of this patent
Estimating the term…
Abstract
A protection circuit to provide suitable disabling control signals to a microprocessor and to an electronic memory to prevent the loss of stored data from the memory during periods of power line interruption or unacceptable power deviations.
Claims7
In a system including an electronic memory and a microprocessor to control the reading or writing of data into said memory, a protection circuit to prevent the loss or alteration of memory data as a result of power line interruptions, said protection circuit comprising:
- power level detecting means having input and output terminal means, said level detecting means sampling the line power at said input terminal means thereof,
- first and second multivibrator devices connected to said output terminal means of said level detecting means, said first multivibrator device responsive to increasing power levels and said second multivibrator device responsive to decreasing power levels, and
- microprocessor and memory control gates connected to said first and second multivibrator devices in order to receive output signals therefrom that are indicative of either an out of tolerance power line interruption or in tolerance power line stabilization,
- said microprocessor and memory control gates adapted to selectively apply respective control signals to said microprocessor and to said memory to, thereby, inhibit the reading or writing of data into said memory and to maintain said microprocessor in a reset mode of operation during the occurrence of undesirable power line interruptions.
A protection circuit to disable each of an electronic memory and an associated microprocessor control circuit during an interval of input line disturbances, said protection circuit including:
- power line detection means connected to an input power line to sense input line disturbances,
- first and second monostable means connected to output terminal means of said power level detection means to receive signals therefrom,
- said first monostable means responsive to input power coming up line disturbances and said second monostable means responsive to input power going down line disturbances, and
- control gating means respectively connected between said first and second monostable means and said electronic memory and microprocessor control circuit,
- said control gating means receiving signals from said first and second monostable means that are indicative of either a power coming up or power going down disturbance, whereby said control gating means applies control signals to inhibit the reading and writing of said memory and to delay the operation of said microprocessor control circuit during the occurrence of the power line disturbances.
Dependencies are inferred from the claim text.