Timer controlled valve

A timed controller comprising

• a valve body having a plurality of ports,
• a valve spool mounted in said body for motion between a first position in which the spool interconnects a first pair of said ports and a second position in which the spool interconnects a second pair of said ports,
• a reversible motor connected to drive said valve spool between said first and second positions, first and second motor control circuits for driving said motor in first and second directions respectively,
• first timer controlled means for energizing said first motor control circuit,
• limit switch means responsive to said valve spool for de-energizing said first motor control circuit,
• reversing means for establishing said second motor control circuit,
• second timer controlled means for energizing said second motor control circuit,
• limit switch means responsive to said valve spool for de-energizing said second motor control circuit,
• said first and second timer controlled means comprising a clock driven actuator carrier, first and second actuators mounted to said carrier, for motion along first and second mutually displaced paths respectively, first and second enabling switches in said first and second motor control circuits respectively, said first and second enabling switches each having an operator arm positioned in an individual one of the paths of said actuators.

An automatic self-cycling timer controlled valve comprising

• a valve body,
• a valve spool movably mounted in the body,
• reversible motor means for driving said spool in one direction or another,
• first and second motor circuit means for energizing said motor in first and second directions respectively,
• timing means for automatically and cyclically enabling said first and second circuit means at times respectively delayed by selected time intervals after disablement of the other of said circuit means, and
• (a) limit switch means comprising
• limit means responsive to attainment of a first position by said valve spool for disabling one of said motor circuit means, and limit means responsive to attainment by said spool of a second position for disabling said other circuit means.

A timer controlled valve comprising

• a valve body,
• a valve spool movably mounted in the body,
• a reversible motor for driving said spool in one direction or another,
• first and second motor circuit means for energizing said motor in first and second directions respectively,
• timing means for sequentially enabling said first and second circuit means,
• a limit switch comprising
• limit means responsive to attainment of a first position by said valve spool for disabling one of said motor circuit means, and limit means responsive to attainment by said spool of a second position for disabling said other circuit means,
• said first circuit means including a power supply,
• a first enabling switch and a first pair of relay contacts connected in circuit with said motor, said second circuit means including a power supply,
• a second enablinhg switch and a second pair of relay contacts connected in circuit with said motor,
• a relay coil coupled with said contacts and connected in circuit with said last mentioned power supply and said second switch, and
• said timing means comprising first and second switch actuators positioned to operate said first and second enabling switches at mutually different times.

A timer controlled valve comprising

• a valve body having a plurality of valve ports therein,
• a valve chamber within said valve body and in communication with said valve ports,
• a valve spool movably mounted for motion within said chamber to selectively block and unblock different ones of said ports,
• a reversible motor,
• means for connecting said motor to drive said valve spool in one direction or another,
• a limit switch actuator connected with said valve spool for motion therewith,
• first and second limit switches,
• said limit switch actuator including first and second actuator legs connected to operate said first and second limit switches respectively as said valve spool moves to first and second positions respectively,
• first and second circuits for respectively energizing said motor for operation in one direction or another,
• said first and second limit switches being connected in said first and second circuits respectively,
• timing means for sequentially enabling said first and second circuits, one after the other,
• said timing means comprising a timer dial,
• first and second actuators carried by said dial for motion in first and second mutually displaced paths,
• first and second enabling switches respectively connected in said first and second circuits, said enabling switches including first and second enabling switch operators positioned in said first and second paths respectively.

A timed controller comprising

• a valve body having a plurality of ports,
• a valve spool mounted in said body for motion between a first position in which the spool interconnects a first pair of ports and a second position in which the spool interconnects a second pair of ports,
• a reversible motor connected to drive said valve spool between said first and second positions,
• first and second motor control circuits for driving said motor in first and second directions respectively,
• first timer controlled means for energizing said first motor control circuit,
• limit switch means responsive to said valve spool for de-energizing said first motor control circuit,
• second timer controlled means for energizing said second motor control circuit,
• limit switch means responsive to said valve spool for de-energizing said second motor control circuit,
• motor reversing means operable between a first condition for establishing said first motor control circuit and a second condition for establishing said second motor control circuit and breaking said first motor control circuit,
• said second timer controlled means including means for operating said motor reversing means between said first and second conditions, said first and second timer controlled means comprising first and second enabling switches connected in said first and second motor control circuits respectively, and a timer driven actuating means for sequentially actuating said enabling switches.

A timed controller comprising

• a valve body having a plurality of ports,
• a valve spool mounted in said body for motion between a first position in which the spool interconnects a first pair of ports and a second position in which the spool interconnects a second pair of ports,
• a reversible motor connected to drive said valve spool between said first and second positions,
• first and second motor control circuits for driving said motor in first and second directions respectively,
• first timer controlled means for energizing said first motor control circuit,
• limit switch means responsive to said valve spool for de-energizing said first motor control circuit,
• second timer controlled means for energizing said second motor control circuit,
• limit switch means responsive to said valve spool for de-energizing said second motor control circuit,
• motor reversing means operable between a first condition for establishing said first motor control circuit and a second condition for establishing said second motor control circuit and breaking said first motor control circuit,
• said second timer controlled means including means for operating said motor reversing means between said first and second conditions,
• said motor reversing means comprising a relay having a first set of contacts in said first motor control circuit,
• a second set of contacts in said second motor control circuit and a coil connected to be energized by said second timer controlled means,
• said first and second timer controlled means comprising a timer driven actuator carrier,
• first and second actuators mounted to said carrier for motion through first and second paths, and first and second enabling switches connected in said first and second motor control circuits respectively and having respective enabling switch operators positioned in said first and second paths.