Microprocessor for an automatic word-processing system

A microprocessor which communicates with a plurality of peripheral devices via a data bus and an instruction word bus, said microprocessor having a read-only-memory (hereinafter abbreviated ROM) which generates a plurality of instruction words on said instruction word bus in response to a corresponding ROM address, said microprocessor including an arithmetic logic unit (hereinafter abbreviated ALU) for performing arithmetic and logic functions, said microprocessor further including a plurality of addressable general purpose data storage registers, each of said instruction words being applied in parallel to said peripheral devices, said ROM, said ALU and said general purpose registers, said combination comprising:

• means for addressing said peripheral devices,
• means within each of said peripheral devices which is responsive to said means for addressing and is further responsive to instruction words transmitted over said instruction word bus to effect a predetermined operation when a control command is specified by said instruction words and to provide a status condition when a status check command is specified by said instruction words,
• means responsive to said status condition to specify a predetermined succeeding ROM address to be applied to said ROM,
• means within said ALU and said general purpose data storage registers responsive to instruction words to effect a predetermined data processing operation on data transmitted over said data bus from said peripheral devices when a data processing command is specified by said instruction words and to provide a test condition result when a test data command is specified by said instruction words,
• means responsive to said instruction words for determining which general purpose register will have its contents processed by said ALU and
• means responsive to said test condition result to specify a predetermined succeeding ROM address to be applied to said ROM.