Balancing the utilization of I/O system processors

An input/output processing system for controlling input/output operations during the concurrent execution of a plurality of processes, said system including a plurality of modules, said modules including an input/output memory module and a plurality of individual input/output processor modules, a main memory module operative to generate signals for specifying initiation of an input/output operation at a particular priority level and a system interface unit having a plurality of ports, each connected to a different one of said plurality of modules, said system interface unit comprising:

• a plurality of interrupt processing circuit means, each connected to a different one of said plurality of input/output processor modules for processing on a priority basis interrupt requests received by the processor module;
• intercommunication network means connected to each of said plurality of interrupt processing circuit means for enabling communication between said plurality of processor modules;
• each of said plurality of processor modules comprising:
• control register means for controlling the execution sequence of said processes, said control register means including a plurality of interrupt bit positions, each for designating the presence of an outstanding interrupt request at one of a number of different priority levels;
• and,
• control means coupled to receive interrupt request signals from said interrupt logic circuit means associated therewith;
• said input/output memory module including a plurality of storage locations, a group of said storage locations defining a queue for storing entries designating new processes to be initiated;
• the interrupt processing circuit means of one of said plurality of input/output processor modules in response to said signals from said main memory module being operative to apply interrupt request signals to said one processor module, said control means being operative to generate a sequence of signals for switching of a predetermined one of said interrupt bit positions of said control register means to a predetermined state indicating the presence of an interrupt at said particular priority level and storing an entry in said queue of said input/output memory module, and
• said intercommunication means being conditioned by signals of said sequence to apply high priority type interrupt request signals to the interrupt processing circuit means of said another one of said plurality of processor modules, said circuit means conditioning said control means of said another processor module to generate signals for switching said predetermined one of said interrupt bit positions to said predetermined state indicating the presence of said interrupt at said particular priority level enabling the least busy processor module of said plurality to initiate said input/output operation thereby balancing the utilization of said input/output processor modules.

An input/output processing system for controlling input/output operations during the concurrent execution of a plurality of input/output processes, said system including a plurality of modules, said modules including a local memory module, a main memory module and n number of individual input/output processor modules, a host processor module operative to apply to said main memory module connect signals for specifying the initiation of an input/output operation at a designated priority level and a system interface unit having a plurality of ports, each connected to a different one of said plurality of modules, said system interface unit comprising:

• n number of interrupt processing logic circuits, one connected to a different one of said number of input/output processor modules for processing interrupt requests received by the processor module on a priority basis;
• intercommunication network means connected to each of said number of interrupt processing logic circuits for enabling communication between said number of processor modules;
• each of said number of processor modules comprising:
• a process control register for controlling the execution sequence of said processes, said process control register including a plurality of interrupt bit positions, each for designating the presence of an outstanding interrupt request at a predetermined one of a number of different priority levels;
• and,
• microprogrammed control means coupled to receive interrupt request signals from said interrupt logic circuits of said system interface unit associated therewith;
• and
• said local memory module including a plurality of storage locations, a group of said storage locations and a queue for storing entires designating new input/output processes to be initiated;
• the interrupt processing logic circuits of a first one of said number of input/output processor modules in response to connect signals from said main memory module being operative to apply interrupt request signals to said first processor module, said microprogrammed control means being operative to generate a sequence of signals for switching of one of said interrupt bit positions to a predetermined state indicating the presence of an interrupt at said designated level and for storing an entry in said queue of said local memory module, and
• said processor intercommunication means being conditioned by said signals of said sequence to apply high priority type interrupt request signals to the interrupt processing logic circuits of said another one of said number of processor modules, said circuits conditioning said microprogrammed control means of another processor module to generate signals for switching a predetermined one of said interrupt bit positions to said predetermined state indicating the presence of said interrupt request at said designated priority level to enable the least busy processor module of said number to initiate said input/output operation thereby balancing the utilization of said number of input/output processor modules.