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AssigneeMicro-Bit Corporation
InventorFloyd O. Arntz
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A buried junction MOS memory capacitor target device for electron beam addressable READ/WRITE memories is described along with a method of using the same. The memory capacitor target structure comprises a planar semiconductor substrate of various degrees of complexity having a highly conducting coating providing a low resistance ohmic contact to the substrate backside and an N-type planar semiconductor overlayer forming with the substrate topside a bipolar detector junction. An insulating layer overlies the N-type layer and a conducting coating overlies the insulating layer. The device is employed with an electron beam of sufficient energy to penetrate the latter two layers and to produce carrier-pairs in the N-type overlayer. Electrical access to the device is provided by one contact to the substrate backside and one contact to the conducting coating overlying the insulator. Means are provided within the semiconducting portion of the device for limiting the electrostatic potential difference developed across the bipolar detector junction as a result of changes in the potentials applied to the electrical contacts. This may be achieved by fabricating the semiconducting portion of the device to provide for the occurrance of avalanche conduction within the detector junction whenever the reverse polarity potential difference across the junction exceeds a desired value. Alternatively the reach through effect commonly observed in thin base bipolar transistors when the collector-base potential difference exceeds a critical value can be employed to limit the reverse potential developed across the bipolar detector junction. This may be achieved by employing a planar semiconducting substrate comprised by a thin P-type layer overlying an N-type layer. In operation the design affords a means for applying the desired potential differences across the insulator for the various steps of memory operation and also affords a means for developing a desired reverse polarity potential difference across the buried bipolar detector junction for the duration of the read process.
A new and improved buried junction metal-insulator-semiconductor memory capacitor target structure for electron beam addressable memories comprising a first planar semiconductor substrate layer having conductive means engaging one of the surfaces thereof for providing electrical connection to said first semiconductor layer, at least a second planar semiconductor layer of opposite conductivity type from said first semiconductor layer juxtaposed to a planar surface of said first semiconductor substrate layer, said first and second layers forming a bipolar junction, an insulating layer overlying said second semiconductor layer and a conducting surface overlying said insulating layer, said conducting surface having means for providing electrical connection thereto, enclosure means for isolating and reducing to a minimum reverse current flow at the perimeter of the bipolar junction during the READ of data and means within the memory capacitor structure for limiting internally the magnitude of the reverse current potential built up across the bipolar junction upon application of a reverse polarity potential across the structure.
In a new and improved method for recording and readout of data with an electron beam addressable memory employing a planar metal-insulator-semiconductor memory capacitor structure having a pair of opposed load terminals and a first semiconductor layer of a first conductivity type forming a bipolar junction with a second semiconductor substrate layer of opposite conductivity type from said first semiconductor layer, and wherein the electric charges are stored in the insulator layer at selected information storage locations on the planar surface of the memory capacitor device while leaving other selected information storage locations free of electric charges to thereby record data on the memory capacitor device for subsequent read-out, the writing and removal of electric charges with subsequent read-out of the data thus recorded requiring the simultaneous application of a bias potential of suitable polarity and magnitude across the memory capacitor device opposed load terminals together with the probing of the selected information storage locations with a finely focused electron beam of suitable energy level to penetrate into the first semiconductor layer at the selected information storage location, and during read-out capacitively coupling the resultant reverse bipolar junction current flow produced at the selected information storage locations as a result of the combined effect of the bias potential and the penetrating electron beam through the pair of opposed load terminals to provide an output indication of the character of the data stored at the location being probed;
A method for read-out of data stored in a metal-insulator-semiconductor memory capacitor structure having a gate electrode and an underlying semiconductor substrate and wherein a predetermined read-out potential magnitude and polarity is established across the memory capacitor while discrete storage sites are interrogated by an electron beam probe and the magnitude of the resultant electron-hole memory capacitor discharge current obtained from probing a particular site with the electron beam is indicative of the character of data stored at the site;
Dependencies are inferred from the claim text.