Insulated gate type field effect transistors

An insulated gate type field effect transistor comprising a semiconductor substrate;

• spaced-apart source and drain regions formed at one surface of said semiconductor substrate;
• a first insulating film overlying the surface of said substrate between said source and drain regions;
• a polycrystalline semiconductor gate layer disposed over said first insulating film and having a deliberately formed inverted frustum shape;
• the top surface of the inverted frustum being at a different level from the level of the source and drain regions and the outer peripheral edges of the projection of the top surface of the inverted frustum onto the substrate being substantially coextensive with the inner peripheral edges of the source and drain regions;
• source, drain and gate electrodes formed on said source region, said drain region and said polycrystalline semiconductor gate layer, respectively, and second insulating films formed over substantially the entire side surface of said polycrystalline semiconductor gate layer between said gate electrode and said source electrode and between said gate electrode and said drain electrode and extending to and covering the top surface areas of the substrate surrounding the gate layer, said last mentioned top surface areas being substantially defined by projecting the top peripheral surface of said inverted frustum gate layer down upon the top surface of the substrate whereby horizontal spacing between adjacent electrodes is essentially zero and parasitic capacitive coupling between the electrodes is minimized.