Digital processor system with simultaneous branch and OP code function

An electronic digital processor fabricated in a single LSI semiconductor device, including a large read-only-memory for storing instruction codes of word length of N bits, addressing circuitry for generating addresses having a given number of bits greater than N/2 for the read-only-memory by either sequencing a program counter when a branch instruction is not present or by branching to an address contained in a branch instruction code when present, the processor including an arithmetic unit having an input, a data memory having an output, and logic means responsive to an opcode for controlling transfer of data from the output of said data memory to the input of the arithmetic unit the improvement comprising means for generating an opcode at the same time that a branch instruction code is executed in the addressing circuitry, wherein parts of the branch instruction code used for the branch address also function as said opcode thereby causing data to be transferred from the output of the data memory to the input of the arithmetic unit by said logic means.