Fast switching Darlington circuit

A fast switching darlington output circuit comprising first and second superposed semiconductor layers of first conductivity type, said second layer having a higher resistivity than said first layer;

• a third semiconductor layer having opposite conductivity type on said second layer;
• said second and third layers providing a common collector and base region respectively for each of first, second and third transistors;
• a first region of said opposite conductivity type in said third layer and extending to the outer surface thereof, said first region having said opposite conductivity type and lower resistivity than said third layer;
• three further regions having said first conductivity type, first and second ones of said further regions located in said third layer and extending to said outer surface thereof, the third further region disposed in said first region and extending to the outer surface of said third layer;
• said two further regions providing emitter regions of said first and second transistors respectively and said third further region providing an emitter region of said third transistor.