Read only memory utilizing charge coupled device structures

A read only memory comprising a charge coupled device shift register having a semiconductor substrate defining a channel overlaid by phase electrodes spanned and insulated from said channel for serial propagation along toward an output end of said channel of charge packets introduced in said channel;

• said shift register having a plurality of stages each defined by a plurality of adjacent phase electrodes;
• charge source means spaced from and extending lengthwise of said channel;
• first charge storage means including first respective charge storage regions defined between said charge source means and a first phase electrode of each of said stages, said first respective charge storage regions being arranged in a first predetermined pattern of different charge storage capacities;
• second charge storage means including second respective charge storage regions defined between said charge source means and a second phase electrode of each of said stages, said second respective charge storage regions being arranged in a second predetermined pattern of different charge storage capacities;
• said first and second charge storage means also including first and second storage gate means respectively;
• said first storage gate means overlying and insulated from said first storage regions, said second storage gate means overlying and insulated from said second storage regions;
• transfer gate means insulated from said substrate;
• said transfer gate means and said first storage gate means together enabling simultaneous transfer of charge from said charge source means to said first charge storage regions, said transfer gate means and said second storage gate means together enabling simultaneous transfer of charge from said charge source means to said second charge storage regions;
• said first storage gate means and said first phase electrodes together enabling subsequent simultaneous transfer of said charge packets from said first storage regions to said channel beneath corresponding ones of said first phase electrodes, said second storage gate means and said second phase electrodes together enabling subsequent simultaneous transfer of said storage packets from said second storage region into said channel beneath corresponding ones of said second phase electrodes.