Wide acquisition range MSK demodulator input circuit
AssigneeRCA Corporation
InventorJames M. Keelty
Life of this patent
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Abstract
An input circuit for a wide acquisition range minimum shift keying demodulator includes a pair of phase-locked loops (PLL). Each PLL is designed to receive from a frequency doubler a respective one of two discrete spectral lines in the frequency spectrum separated by a frequency equal to the bit rate. Each PLL operates at one of three frequencies including its own search position frequency and the search position frequency of the other PLL plus or minus the bit rate. A logic decision circuit responsive to the PLLs operates with a frequency synthesizer connected to a mixer at the input of the doubler so that when one PLL locks to one spectral line, the other PLL is operated at its respective frequencies to lock to the other spectral line.
Claims7
An input circuit for a wide acquisition range minimum shift keying demodulator adapted to scan an input signal having a region of frequency uncertainty and a given bit rate R, said circuit comprising:
- a mixer, a filter and a frequency doubler coupled in that order and responsive to said input signal being applied to said mixer, said doubler adapted to produce two spectral lines,
- a pair of PLLs each coupled to the output of said doubler, each of said PLLs adapted to monitor half of the said region of frequency uncertainty, each of said PLLs comprising a voltage controlled oscillator (VCO) and a programmable divider located at the output of the VCO and adapted to allow the corresponding PLL to assume at least two operating frequencies, and a lock detector adapted to permit the corresponding PLL to lock to one of the two spectral lines,
- a frequency synthesizer coupled to said mixer and adapted to scan the input signal until one of said PLLs locks to one of the spectral lines,
- a logic decision circuit coupled to each of said PLLs and to said synthesizer to respond to the state of the lock detector of the PLLs to control the divider of each of said PLLs to make the latter assume one or the other of said operating frequencies and to stop the scanning operation of the frequency synthesizer,
- whereby the frequency synthesizer scans the input signal until one PLL locks to one of the spectral lines, the logic circuit being responsive to the locked condition of said one PLL to command the divider of the other PLL to sequentially assume one of its operating frequencies until the said other PLL locks to the second of said lines.
In combination,
- input means providing a signal having first and second discrete spectral lines in the frequency spectrum,
- a pair of phase locked loops (PLL) coupled to said input means each settable to at least two operating frequencies,
- means coupled to said input means for scanning the frequency of said signal until one of said PLLs locks to one of said spectral lines, and
- decision circuit means responsive to the locking of said one PLL to one of said spectral lines to cause said second PLL to assume one or the other of its operating frequencies to lock said second PLL to said second spectral line.
Dependencies are inferred from the claim text.