Presettable rate multiplier

A rate multiplier, having a plurality of ordered rate inputs and a clock input, for generating an output frequency f.sub.out which is a fraction of an input frequency f.sub.in, comprising:

• a series of connected counting stages, each counting stage being clocked by the input clock and having a preset input which, when enabled, locks the counting stage into a given output state which inhibits the counting stage from counting when clocked, and
• logic circuit means, having the ordered rate inputs as inputs and having outputs connected to the series of connected counting stages, for controlling the enabling of the preset input of each counting stage so that no preset input can be enabled unless the preset inputs of all previous counting stages in the series are also enabled.