Voltage regulator
AssigneeHoneywell Inc.
InventorsL. V. Westbrook, R. L. Payne
Life of this patent
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Abstract
A voltage regulator using CMOS (complementary metal-oxide semiconductor) signal processing. A sample of the regulator's output voltage is supplied to a voltage-controlled oscillator which produces an unsymmetrical output waveform which in turn drives a switching transistor. The switching transistor, when ON, supplies power from an unregulated source to a load circuit. Any deviation in the regulated output voltage from the desired level causes a compensating change in the ratio of ON to OFF times of the switching transistor.
Claims4
An integrated circuit voltage regulator for converting an unregulated potential applied to an input conductor into a regulated potential supplied to an output conductor comprising, in combination:
- at least first, second and third insulated-gate field-effect transistors each having a gate electrode and a transconductive channel,
- means for applying a potential having an amplitude related to said regulated potential to the gate of said first transistor,
- a timing capacitor,
- means for charging said timing capacitor through the series combination of the channels of said first and second transistors,
- means for discharging said timing capacitor through the series combination of a substantially constant resistance and the channel of said third transistor,
- and means for reversing the conductivity states of said second and third transistors when the voltage across said timing capacitor reaches a predetermined value.
An integrated circuit voltage regulator for converting an unregulated voltage from a power source into a regulated voltage supplied to a load circuit comprising, in combination
- four insulated gate field-effect transistors each having a gate electrode and a transconductive channel,
- means connecting the channels of said first, second and third transistors in series across said power source, said second and third transistors being of opposite conductivity type,
- a timing capacitor connected between the junction of said second and third transistors and the gates of both said second and third transistors,
- a pair of cascaded inverters having their input connected to said junction point and their output connected to the gates of said second and third transistors,
- a switching transistor having its channel connected to supply power from said source to said load and its gate connected to the output of said cascaded inverters, and
- a feedback connection between said load circuit and the gate of said first transistor.
Dependencies are inferred from the claim text.