Apparatus and method for storing parity encoded data from a plurality of input/output sources

A method of detecting and correcting errors in groups of signals received from any one of a plurality of data handling devices connected to a bus network for storage in a memory subsystem containing encoder and decoder circuits, each of said groups of signals including a plurality of data bit signals and at least one parity bit signal for indicating the validity of said plurality of data bit signals, said method comprising the steps of:

• receiving a group of signals to be stored in said memory from one of said devices for writing into said memory during a memory cycle of operation;
• generating a group of check code bit signals by said encoder circuits from said plurality of data bit signals and said one parity bit signal of said group and forcing a number of said check code bit signals to a predetermined state when said one parity bit signal indicates that said data bit signals received from said one device are in error;
• storing only said data bit signals and said check bit signals of said group in said memory during said memory cycle of operation;
• and,
• generating a plurality of syndrome signals by said decoder circuits for locating an error in said data bit signals of said group of signals, the location of said error being established by said data bit signals and said check code bit signals read out from said memory during a succeeding memory cycle of operation and forcing said plurality of syndrome signals to have a first predetermined characteristic for signaling when said group of data bit signals had incorrect parity when written into said memory enabling detection of incorrect signals without decreasing the operating speed of said data handling devices.

In a data processing system including a memory including a plurality of word locations, an encoder, a decoder and error indicator circuits, a plurality of peripheral devices, a central processing unit, each connected to transmit and receive words over a bus network to and from said memory, each of said words including a number of bytes and a corresponding number of parity bits, a method of detecting errors during the performance of a partial write operation wherein said partial write operation involves replacement of one of said number of said bytes of a word read out from one of said plurality of addressable locations with a byte applied to said bus network, said method comprising the steps of:

• receiving a byte write signal from said bus network indicating when said memory is to perform said partial write operation;
• generating an output error signal by said error indicator circuits in response to a plurality of syndrome signals from said decoder indicating the presence of an uncorrectable error in one of said words read out from one of said memory locations during a read portion of said partial write operation;
• applying said output error signal and said byte write signal to said encoder;
• generating by said encoder a group of check code bits derived from a first byte applied to said bus and a second byte read out from said one of said memory locations during said read portion;
• forcing by said encoder a number of said check code bit signals to a predetermined state in response to said output error signal;
• and,
• writing said check code bit signals and said first and second bytes into one of said memory locations during a write portion of said partial write operation for enabling detection of uncorrectable error conditions during a subsequent memory cycle of operation by said decoder forcing said syndrome signals to have a first predetermined characteristic.

A data processing system including at least one memory unit central processing unit and a plurality of peripheral devices each being connected to a bus for transmitting and receiving words to and from said memory unit each of said words including a number of bytes and a corresponding number of parity bits for indicating the validity of one of said bytes associated therewith, said memory unit comprising:

• an addressable memory having a plurality of word locations;
• input means connected to said bus for receiving any one of said words from any one of said devices and said central processing unit for storage in one of said word locations during a memory cycle of operation;
• an encoder connected to said input means, said encoder being operative to generate a group of check code bit signals from said any one of said words immediately upon being received from said bus, said encoder forcing a number of said check code bit signals to a predetermined state when conditioned by one of said number of parity bits which designates that a corresponding byte is in error;
• means connected to said encoder and to said input means for applying said number of bytes of said nay one of said words and said group of check code bit signals to said memory for writing into one of said memory locations during said memory cycle of operation;
• and,
• a decoder connected to said memory, said decoder generating a plurality of syndrome signals for locating errors in said number of bytes of said one of said memory location when read out during a subsequent memory cycle of operation, said decoder being conditioned by said number of said check code bits being in said predetermined state to cause said plurality of syndrome signals to have a first predetermined characteristic for signaling that one of said bytes had bad parity when written into said memory enabling the storage of each of said words to proceed without decreasing the operation speed of said system.