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US 4,072,545 AGranted
Raised source and drain igfet device fabrication
AssigneeInternational Business Machines Corporation
InventorFrancisco H. De La Moneda
Life of this patent
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Abstract
Disclosed is an integrated circuit field effect transistor having a source and drain which protrude above the silicon substrate so as to create shallow junctions with the substrate while maintaining a relatively low sheet resistivity in the region. Two self-aligned source and drain fabrication processes are disclosed for the device. The first process yields a polysilicon field shield and the second process yields a field region composed of thermal silicon dioxide.
Claims8
A process for making an insulated gate field effect transistor device having shallow source and drain junctions, comprising the steps of:
- growing a first insulating layer of a first thickness on the surface of a silicon substrate of a first conductivity type;
- forming a first opening and a second opening spaced from said first opening in said insulating layer in the intended location for the source and drain respectively of the device;
- depositing a layer of silicon of a second conductivity type over the exposed surfaces of said insulating layer and said substrate;
- said silicon layer being formed in a polycrystalline phase in those regions lying over said insulating layer, with a first polysilicon region formed over the portion of said insulating layer between said first and said second opening and a second polysilicon region being formed over the portion of said insulating layer surrounding said first and said second openings;
- said silicon layer formed in an epitaxial monocrystalline phase in those regions lying over said exposed semiconductor substrate, with a first epitaxial region formed over said first opening and a second epitaxial region formed over said second opening;
- etching a first trough between said first polycrystalline silicon region and said first epitaxial silicon region and a second trough between said first polycrystalline silicon region and said second epitaxial silicon region;
- doping the surface of said substrate exposed by said first trough and said second trough with a dopant of said second conductivity type;
- growing a second insulating layer of a second thickness greater than said first thickness in said first and second troughs;
- forming electrical contacts with said first polycrystalline silicon region as a gate electrode, with said first epitaxial region as a source electrode, and with said second epitaxial region as a drain electrode;
- whereby an insulated gate field effect transistor device is formed in a process which decouples the fabrication of the source and drain P-N junctions from their conductivity interconnections.
7 more elements
A process for fabricating an integrated circuit field effect transistor device having shallow source and drain regions, comprising the steps of:
- growing a silicon nitride layer on the surface of a silicon substrate;
- etching said silicon nitride layer so as to leave a first silicon nitride region and a second silicon nitride region spaced from said first silicon nitride region on the surface of said substrate;
- growing a first thermal oxide layer on the exposed portions of the surface of said silicon substrate so as to form a first thermal oxide region surrounding said first and second silicon nitride regions and a second thermal oxide region between said first and said second silicon nitride regions;
- etching said second thermal oxide region so as to expose the surface of said substrate beneath same;
- growing a second, thin thermal oxide layer between said first and said second silicon nitride regions;
- etching said first and said second silicon nitride regions so as to expose the surface of said silicon wafer thereunder as first and second window regions;
- depositing a silicon layer on all exposed surfaces;
- said silicon layer forming the polycrystalline silicon phase in those regions over said first thermal oxide layer and said thin thermal oxide layer;
- said silicon layer forming a first epitaxial monocrystalline region over said first window region exposing said silicon substrate and a second epitaxial monocrystalline region over said second window region exposing said silicon substrate;
- etching a first trough between said first epitaxial region and said thin oxide region and a second trough between said second epitaxial region and said thin oxide region;
- doping the surface of said substrate exposed by said first and second troughs with a dopant of said second conductivity type;
- growing a third thermal oxide layer thicker than said second thermal oxide layer, in said first and second troughs;
- forming an electrical contact with each polycrystalline silicon region;
- whereby an insulated gate field effect transistor is formed in a process which decouples the fabrication of the shallow source and drain junctions from their conductivity interconnections.
11 more elements
Dependencies are inferred from the claim text.