Current mode multiple-generating register
AssigneeHoneywell Information Systems Inc.
InventorHomer Warner Miller
Life of this patent
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Abstract
A multiple-generating register generates one of several possible multiples of a binary number which is input thereto depending upon the informational content of a 3-bit control signal. For each data stage there exists a data selector circuit, a master/slave circuit, and an output buffer circuit. The device can be configured as an inverting shift register for test and diagnostic purposes. The device is implemented in current mode logic, and a portion of the circuitry operates on differential level signals for increased operational speed and efficiency.
Claims6
An improved current mode muliple-generating register for generating multiples of a first binary number which is input thereto, said register being provided with non-functional test (NFT) capabilities, said register comprising:
- a control circuit comprising a first portion responsive to a 3-bit control signal Y1 Y2 Y4 and a second portion responsive to a first control signal NFTR and to a second control signal NFTS;
- a clock circuit responsive to a clock signal $ and to a clock-enable signal .cent.S;
- a plurality of data stages, each of which is responsive to a respective bit of said first binary number, each of said data stages further comprising
- a data selector circuit responsive to said respective bit of said first binary number and further responsive to said control circuit,
- a master/slave register, said master/slave register being responsive to said clock circuit and further responsive to said data selector circuit, and
- an output buffer circuit responsive to said master/slave register,
- whereby said plurality of data stages generate a second binary number which is a multiple of said first binary number in response to said 3-bit control signal.
Dependencies are inferred from the claim text.