MOS input buffer with hysteresis

#In recent years it has become possible to implement many complex logic functions on a single semiconductor die utilizing the MOS technology, wherein thousands of MOSFETS (metal oxide semiconductor field effect transistor) or IGFETS (insulated gate field effect transistor), as they are also commonly called are utilized to implement such products as 4096 bit decoded random access memories, 8192 bit readonly only memories, and complete microprocessors. Input buffer circuits are required on all of these circuits in order to permit the MOS LSI chips to receive digital signals from the environment in which it will operate. Most of the input buffer circuits have been inverters or latchers of various types. In designing MOS input buffer circuits, the main problems to be overcome by the circuit designer have been to provide input buffer circuits which produce adequate logical "1" and logical "0" output levels (to be utilized by other circuitry within the MOS LSI circuit) in response to worst case input "1" and "0" logic levels over the ranges of permissible variations in power supply voltage levels, MOSFET threshold voltages and other MOS processing parameters. Although many MOS input buffer circuits have been designed, no one input buffer circuit has proven completely satisfactory for a wide range of practical applications.

#It is an object of this invention to provide a buffer circuit having a hysteresis characteristic in which the positive gain portion of the switching characteristic extends substantially all the way between the high and low output voltage levels.

#It is another object of the invention to provide a buffer circuit having a switching characteristic having minimum dependence upon voltage supply variations and manufacturing parameter variations.

#FIG. 1 is a schematic diagram of a preferred embodiment of the invention.

#FIG. 2 is a graph illustrating a switching characteristic of the circuit of FIG. 1.

#FIG. 3 is a diagram illustrating an application of the input buffer circuit of FIG. 1 in an MOS LSI semiconductor die.

#Referring to FIG. 1, input buffer 10 has an input 11 and an output 12, and is energized by V.sub.DD conductor 13 and ground conductor 20. Input node 11 is connected to the gate electrode of input MOSFET 16, which is an enhancement mode MOSFET. The drain of enhancement mode MOSFET 16 is connected to node 12, and its source is connected to node 18. Those skilled in the art will recognize that MOSFETs are of two types: enhancement mode and depletion mode. An enhancement mode MOSFET is in off condition if its gate and source are at the same voltage. For example, if MOSFET 16 is an N-channel MOSFET, it might have a threshold voltage of approximately two volts, meaning that the gate-to-source voltage would have to exceed two volts before the MOSFET would conduct a current between the source and drain electrodes. An N-channel depletion mode MOSFET may be thought of as having a negative threshold voltage, so that when the source and gate are at the same voltage, the negative threshold voltage is exceeded and the device conducts current between its source and drain electrodes. For a more complete discussion of MOSFETs, see "Physics and Technology of Semiconductor Devices," A.S. Grove, John Wiley & Sons, New York, 1957. For a more thorough description of the depletion mode MOSFETs, see "MOSFETs In Circuit Design", by Robert Crawford, McGraw Hill, 1967. Those skilled in the art will recognize that MOSFETs are bilateral devices. That is, the current-carrying terminals (the source and drain) designated source and drain may be interchanged in digital applications. Current can flow in either direction through a MOSFET, depending upon the relative voltages at the gate, source, and drain. In a given circuit, a particular electrode can serve the function of source part of the time and drain at other times.

#Depletion mode MOSFET 19 has its drain connected to node 18, its source connected to ground conductor 20, and its gate connected to V.sub.DD conductor 13C. However, it is not necessary that conductor 13C be connected to exactly the same voltage as conductor 13. Depletion mode MOSFET 17 has its gate connected to output node 12, its source connected to node 18, and its drain connected to conductor 13B, which could also be V.sub.DD volts. The dotted line encompassing MOSFET 17 and indicated by reference numeral 17A indicates that some other resistive device responsive to V.sub.OUT, the voltage at node 12, could be utilized in place of MOSFET 17.

#Depletion load MOSFET 15 has its source and gate connected to node 12, and its drain connected to the source of enhancement mode MOSFET 14. Enhancement mode MOSFET 14 has its gate connected to conductor 13A, which could be at V.sub.DD volts, and its drain connected to conductor 13, which is at V.sub.DD volts.