Data packets distribution loop
AssigneeRCA Corporation
InventorCharles Stewart Warren
Life of this patent
Estimating the term…
Abstract
A data communications or distribution loop has a plurality of computer stations each of which introduces a delay while it examines the header of each circulating packet or block of data. An elastic synchronizing buffer, including a random-access memory, is included in the loop to introduce a delay which, when added to the delays introduced by the stations, equals the period of a packet. The delay introduced by the buffer is automatically adjusted as stations are added to, or removed from, the loop.
Claims10
A synchronizer for inclusion in a data communications system loop in which packets of N information bits circulate together with clock pulses and packet-start pulses in a loop having S stations each of which introduces a delay corresponding with the time of n clock pulses, comprising
- a random access memory,
- an input address counter means counting to N, incremented by each clock pulse and reset by each packet-start pulse, to store successive information bits in successive memory locations, and
- an output address counter means, incremented by each clock pulse and reset upon reaching a count equal to the number N of bits in the packet, to read out information bits successively from successive memory locations,
- whereby the contents of said address counters differ by an amount d so that the memory introduces a delay equal to d clock pulses, which, when added to the number n times S of clock pulse delays introduced by the S stations connected in the loop, is an integral multiple, including unity, of the number of N of bits in each packet.
A data loop communications system, comprising a plurality of stations connected in a loop through which packets of information bits circulate together with clock pulses and packet-start pulses, each of said stations introducing a delay, and
- a synchronizer connected in the communications system loop and including
- a random access memory
- an input address counter means counting to N, incremented by each clock pulse and reset by each packet start pulse, to store successive information bits in successive memory locations, and
- an output address counter means, incremented by each clock pulse and reset upon reaching a count equal to the number of bits in the packet, to read out information bits successively from successive memory locations,
- whereby the contents of said address counters differ by an amount such that the memory introduces a delay, which, when added to the delays introduced by the stations connected in the loop, is an integral multiple, including unity, of the period of a packet.
Dependencies are inferred from the claim text.