Automatic reconfiguration apparatus for input/output processor

In a computer system including a system interface unit coupled to plural processors, plural main memories, a peripheral unit for storing computer programs, an interval timer and a computer program bootload apparatus, the combination which comprises:

• a. first logic means responsive to either intrasystem or extrasystem initialization requests for providing a first logic state indicating a system reconfiguration condition during a start-up phase of a system initialization;
• b. second logic means responsive to said first logic state for selecting one of said plural memories and one of said plural processors to initialize a bootload sequence wherein a computer program stored in said peripheral unit is loaded into said one of said plural memories for execution by said one of said plural processors;
• and
• c. third logic means in electrical communication with said first and said second logic means for automatically and sequentially selecting (n) different configurations of said plural memories and said plural processors in the event of (n) failures to load said computer program within a preset time interval.

A reconfiguration system for controlling the flow of information between plural processors and plural memory units in a computer system having peripheral information storage means, which comprises:

• a. system initialization logic means responsive to an initialization request signal for setting a reconfiguration mode flag;
• b. logic reset means responsive to said flag for placing said reconfiguration system in an initial logic state;
• c. control counter means in electrical communication with said logic reset means and said system initialization means for providing configuration control signals to address selected ones of said plural processors and said plural memories;
• d. mask register means in electrical communication with said logic reset means and said control counter means for routing information signals between said plural processors and said plural memories in accordance with said control signals;
• e. an interval timer in electrical communication with said logic reset means for indicating the expiration of a preset time interval;
• and
• f. reinitialization counter means in electrical communication with said interval timer means, said system initialization logic means and said control counter means for initiating successive bootload operations and controlling the selection of successive communication paths between said plural processors and said plural memories.