Control store organization in a microprogrammed data processing system
AssigneeHoneywell Information Systems Inc.
InventorVirendra S. Negi
Life of this patent
Estimating the term…
Abstract
A control store having a first portion for storing system operation instructions (opcodes), a second portion for storing control store addressing information, wherein the second portion includes a greater number of storage locations than does the first portion in order to efficiently store different control store address information which may be required for the same opcode. Addressing apparatus coupled to address a location in the first portion and any one of at least two corresponding locations in the second portion is provided, thereby minimizing the number of locations required in the first portion of the control store.
Claims10
A data processing system comprising:
- a. means, responsive to a first group of signals, for generating an address including a least significant portion and a most significant portion, said most significant portion having either a first state or a second state;
- b. first storage means having a first plurality of word locations, each of said word locations having a first plurality of bit locations;
- c. second storage means having a first plurality of word locations, each of said word locations having a second plurality of bit locations;
- d. third storage means having a second plurality of word locations, each of said word locations having a second plurality of bit locations, each of said word locations of said third storage means having positions corresponding to those of said second storage means;
- e. wherein said first storage means includes command information for controlling the operation of said system and wherein said second and third storage means includes address information representative in part of said first group of signals;
- f. first means for addressing said first storage means with said least significant portion of said address;
- and,
- g. second means for addressing said second and third storage means with said least significant portion and said most significant portion of said address, said second means for addressing including means for addressing said second storage means if said most significant portion is in said first state and means for addressing said third storage means if said most significant portion is in said second state, whereby the same said command information is addressed when either a said word location in a corresponding location of said second storage means or a said word location in a corresponding location of said third storage means is addressed.
A data processing system comprising:
- a. a first memory having a plurality of locations for storing control words;
- b. a second memory having a plurality of locations for storing address words;
- c. a third memory having a plurality of locations for storing address words;
- d. means, responsive to next address signals, for addressing said first memory and simultaneously therewith addressing either said second memory or said third memory;
- e. wherein said first, second and third memories each have a beginning address, and wherein said locations in each of said memories correspond to each other, each said corresponding location being the same number of locations from their respective beginning address;
- and wherein
- f. said means for addressing further comprising means for enabling the transfer from said memories of a said control word and either one of two different address words, said means for enabling including means for addressing one said corresponding location in said first memory and one said corresponding location in either said second memory or said third memory.
Dependencies are inferred from the claim text.