Current mode simultaneous dual-read/single-write memory device

An improved current mode simultaneous dual-read/single-write memory device comprising:

• a plurality of n data-in circuits, each data-in circuit comprising a data selector circuit and a master latch register, each of said master latch registers generating a true data-in signal and a complement data-in signal,
• a write select circuit responsive to a plurality of write select signals for generating one of m write select commands over m write select lines,
• first and second read select circuits, said first read select circuit being responsive to a plurality of first read select signals for generating one of m first read select command signals, and said second read select circuit being responsive to a plurality of second read select signals for generating one of m second read select command signals,
• a control circuit responsive to a clock signal $ and to a clock enable signal .cent.$, said control circuit generating an output signal to each of said master latch registers and to said write select circuit,
• an m.times.n matrix of memory cells, where m represents the number of words to be stored in said memory cells and n represents the number of bits per word, each cell comprising first and second dual emitter bipolar transistors, the base of each transistor being connected to the collector of the other transistor, resistive means connecting the collector of each transistor to a voltage potential, one emitter of each transistor being connected to one of m write select lines, the remaining emitter of said first transistor being connected to said complement data-in signal of one of said master latch registers, the remaining emitter of said second transistor being connected to the true data-in signal of said master latch register, a first memory cell read enable circuit, said first memory cell read enable circuit responsive to said first read select command signal and being capable of distinguishing between conduction or non-conduction in said first and second transistors, said first memory cell read enable circuit generating a first true readout signal and a first complement readout signal, a second memory cell read enable circuit responsive to said second read select command signal and being capable of distinguishing between conduction or non-conduction in said first and second transistors, said second memory cell read enable circuit generating a second true readout signal and a second complement readout signal,
• first and second sets of n data output buffers, said first set of n buffers being responsive to said first true and complement readout signals from said first memory cell read enable circuit and said second set of n buffers being responsive to said second true and complement readout signals from said second memory cell read enable circuit.