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AssigneeInternational Business Machines Corporation
InventorsKlaus Heuber, Wilfried Klein, Knut Najmann, Siegfried Kurt Wiedmann
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An improved method of operating a monolithic memory together with novel and efficient circuitry for practicing said improved method is disclosed. In a bipolar transistor store, or monolithic memory, in accordance with the invention, a very low current (first level) flows from the load elements to the internal cell nodes in the stand-by mode. During the initial portion of a read cycle, current flows from the bit lines to the cell nodes, in addition to the stand-by current (second level). In the recovery period of the read cycle or write cycle a short pulse is added to the stand-by current (third level), thereby reducing the recovery time. The practice of the invention provides a monolithic memory having minimal power requirements and a substantially reduced cycle time.
In a method of powering a semiconductor storage array wherein the actual flip-flop transistors and the load elements of the storage cell thereof comprise bipolar transistors and wherein the supply voltage is applied in several phases, said method being characterized by the step that (1) a stand-by level current flowing after reading, or writing, in a read, or write cycle subdivided into two phases, is increased for a very short time interval in the cycle by a current increment during a recovery phase of the read, or write cycle, whereby the voltage of the cell node capacitances of the storage cells recover rapidly, and upon termination of said current increment during the recovery phase the current reverts to the stand-by level.
In a method of powering a semiconductor storage array, wherein the actual flip-flop transistors of the storage cells and the load elements of the storage cells comprise bipolar transistors and the supply current is applied in at least two phases, said method being characterized by inclusion of the following step:
A circuit arrangement for powering a storage array having a plurality of word lines and a plurality of storage cells associated with each word line, wherein the emitters of the flip-flop transistors of each of the storage cells are connected to a predetermined one of said plurality of word lines, each of said storage cells including in addition to said flip-flop transistors first and second load transistors, said circuit arrangement being characterized as follows:
In a monolithic storage array circuit having one through n groups of storage cells, each storage cell having first and second cross coupled bipolar flip-flop transistors and first and second collector loads said monolithic storage array circuit including:
Dependencies are inferred from the claim text.