Virtually nonvolatile static random access memory device
AssigneeThe United States of America as represented by the Secretary of the Air Force
InventorsFritz L. Schurmeyer, Charles R. Young
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Abstract
A high density, static, virtually nonvolatile, Random Access Memory (RAM) cell is disclosed in which variable threshold n-channel depletion mode Metal-Nitride-Oxide-Semiconductor (MNOS) transistors are the load devices for a pair of active, n-channel, enhancement mode, Insulated Gate Field Effect Transistors (IGFETs) in a flip-flop circuit. N-channel enhancement mode access transistors also IGFETs connect the cell to the bit line and the bit line. Information is written in, and read, in volatile form conventionally. A +25 volt, 10 msec pulse applied to the gates of the depletion mode MNOS load devices transfers the data from the volatile mode to the nonvolatile mode.
Claims2
A solid state RAM cell for a memory system having a bit line, a bit line, a word line, a gate line, and a drain line, the said cell comprising:
- a. an n-channel substrate;
- b. a first IGFET enhancement mode access transistor fabricated on the said n-channel substrate cooperating with the said bit line and the said word line;
- c. a second IGFET enhancement mode access transistor fabricated on the said n-channel substrate cooperating with the said bit line and the said word line;
- d. a first and a second IGFET enhancement mode, active transistors fabricated on the said n-channel substrate and cooperating with each other to provide a flip-flop;
- e. a first MNOS, IGFET depletion mode variable threshold transistor, fabricated on the said n-channel substrate, having a drain electrode connected to the said drain line, a gate electrode connected to the said gate line and a source electrode;
- f. a second MNOS, IGFET depletion mode variable threshold transistor, fabricated on the said n-channel substrate, having a drain electrode connected to the said drain line, a gate electrode connected to the said gate line, and a source electrode;
- g. means for connecting the said first access transistor and the said flip-flop to the said source electrode of the first variable threshold transistor, and the said second access transistor and the said flip-flop to the said source electrode of the second variable threshold transistor whereby a nonvolatile RAM is provided.
In a random access memory device having enhancement mode active IGFET transistors with depletion mode MNOS variable threshold IGFET loads, all on n-channel material, and with a bit line, a bit line, a drain voltage line, a word line, and a gate line, the method of transferring data conventionally stored in volatile form to non-volatile storage, recovering the data, and erasing the device, comprising the steps of:
- a. applying a positive pulse to the said gate line for transferring the said data stored in volatile form to nonvolatile form;
- b. applying drain voltage, precharging the bit lines, and pulsing the word line to recover the said data after nonvolatile storage;
- and
- c. erasing the said memory device by applying a series of negative pulses to the said gate line.
Dependencies are inferred from the claim text.