Random access memory cell with ion implanted resistor element

A semiconductor integrated circuit comprising first and second MOS transistors each having a source-drain path and a gate, the source-drain path of the first transistor being connected between a first node and a source of logic levels, the gate of the first transistor being connected to a different source of logic levels, the source-drain path of the second transistor being connected between the first node and a voltage supply, an intermittent voltage source coupled to the gate of the second transistor at a second node, and an impedance element connecting the first node to the second node, the impedance element exhibiting a low impedance state when the voltage on the first and second nodes is relatively low and exhibiting a high impedance state when the voltage on the first and second nodes is relatively high.