Data transfer synchronizing circuit
AssigneeMotorola, Inc.
InventorsEdward Clare Hepworth, Rodney Jerome Means
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Abstract
A digital logic circuit synchronizing data transfers between asynchronously clocked data systems. Synchronization is accomplished by three logically interlocked storage elements which respectively record and control (1) the time when data is available for transfer, (2) time when data transfer begins and (3) the time when data transfer is complete. Transfer is accomplished without a loss of data independent of the clock pulse width and frequency relationship of the asynchronously clocked systems.
Claims10
A digital logic circuit for synchronizing the transfer to data between asynchronously clocked data systems comprising:
- a. a first register coupled to a source of data,
- b. a second register coupled to said first register,
- c. first control means for selectively enabling the loading of data from said source of data into said first register, said first control means comprising a first flip-flop, one state of which denotes that data is available for transfer from said first register to said second register,
- d. second control means for selectively enabling the transfer of data from said first register to said second register,
- e. third control means for enabling the transfer of data from said second register to an output,
- f. said third control means including further means for inhibiting said first and second control means until completion of the transfer of data from said second register.
Dependencies are inferred from the claim text.