Sensing circuit for memory cells
AssigneeNippon Telegraph & Telephone Public Corporation
InventorsNobuaki Ieda, Takao Yano
Life of this patent
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Abstract
A weak signal detecting circuit in which a sensing circuit formed with a flip-flop circuit, and bit lines each having connected thereto a plurality of 1-transistor type memory cells, are interconnected by separation transistors for separating them from each other, and in which power supply transistors are inserted between power sources and the bit lines. When the power supply transistors are turned on, the separation transistors are turned off, so that a signal detection can be performed with little power consumption. Further, in such a case, the bit lines are disconnected from the sensing circuit to thereby enable a high-speed and highly sensitive detecting operation to be stably achieved regardless of the number of memory cells.
Claims6
A weak signal detecting circuit comprising:
- a flip-flop circuit composed of first and second MIS transistors having sources connected together and having the drain and gate of one MIS transistor respectively inter-connected to the gate and drain of the other MIS transistor;
- a third MIS transistor connected between the drain of the first MIS transistor and a first bit line so that the drain and source of the third MIS transistor provide a current path therethrough;
- a fourth MIS transistor connected between the drain of the second MIS transistor and a second bit line so that the drain and source of the fourth MIS transistor provide a current path therethrough the gates of the third and fourth MIS transistors being so connected as to be supplied with a first clock signal;
- a fifth MIS transistor having a source connected to the first bit line;
- a sixth MIS transistor having a source connected to the second bit line, the drains of the fifth and sixth MIS transistors being connected together and to a first power source, and their respective gates being so connected as to be supplied with a second clock signal;
- a reference level generating circuit connected to the first and second bit lines;
- a precharge circuit connected to the first and second bit lines;
- a seventh MIS transistor having a drain connected to the sources of the first and second MIS transistors, the source of the seventh MIS transistor being grounded and the gate being so connected as to be supplied with a third clock signal;
- wherein the third and fourth MIS transistors are turned off only during signal detection while being operative throughout the rest of the operation,
- two additional MIS transistors having their sources respectively connected to the drains of the first and second MIS transistors, their drains connected together and to the first power source, and their gates so connected together as to be supplied with a second clock signal, wherein the fifth, sixth and two additional MIS transistors are turned on only during the time that the third and fourth MIS transistors are turned off, and
- wherein the input/output is taken from one of said bit lines.
Dependencies are inferred from the claim text.