Limiter circuit for timing recovery in a high speed digital repeater
AssigneeNorthern Electric Company Limited
InventorBrian Richard Bryden
Life of this patent
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Abstract
A limiter circuit for the extracted timing signal in high speed digital repeaters is disclosed. The conventional emitter-coupled transistor pair limiter is modified by applying to the base of the output transistor the decoupled, attenuated, and delayed signal at the collector of the input transistor. The delay is such that the compensating signal at the base is out-of-phase with respect to the input signal by approximately -5/2.pi.. Experimental determination of delay and attenuation yields optimal phase and amplitude responses which are a significant improvement over those of the conventional limiter.
Claims24
A limiter circuit for a periodic input signal having varying amplitudes, comprising:
- a. first and second switching devices connected and biased to operate in current mode switch operation;
- b. means for applying said input signal to a control electrode of said first switching device;
- c. means, including a series direct current blocking means, connected between an output electrode of said first switching device and a control electrode of said second switching device for applying a delayed, attenuated version of the signal appearing at said output electrode to said control electrode, whereby said delayed, attenuated version has at the control electrode a predetermined amplitude and a predetermined difference in phase with respect to said input signal.
A limiter circuit for a periodic input signal having varying amplitude for limiting the timing sinusoid extracted from a high speed pulse stream and preamplified to have a predetermined minimum operational level, comprising:
- a. a pair of high speed bipolar switching transistors of the same conductivity type, having a common emitter resistor to a common circuit terminal;
- b. means for biasing said transistor pair to operate in non-saturated current mode;
- c. means for coupling said timing sinusoid to the base of one of said pair of switching transistors;
- and
- d. a series connection of d-c blocking means, signal attenuating means and phase shifting means, for coupling the collector of said one of said pair of switching transistors to the base of the other.
Dependencies are inferred from the claim text.