Loading patent…
AssigneeBell Telephone Laboratories, Incorporated
InventorsClair Alan Buzzard, Richard Cyril Gifford, Frank William Lescinsky, Robert Michael Zachok
Estimating the term…
A memory array, having a plurality of intersecting rows and columns, stores digitized speech. Each row and column intersection consists of a binary storage cell for storing one bit of digitized speech. Incoming digitized speech is loaded into columns of the memory array in a plurality of repetitive loading sequences, each loading sequence including: reading out the bits stored in successive rows of binary storage cells, replacing in each successive row of bits, a predetermined one of the bits in the read out row with a successive one of the bits of the digitized speech and writing each read out row of bits including the replaced bit back into the row. Multibit binary grunts (digitized speech segments) stored in the array are read out therefrom by applying the bits of the grunts to time slots in frames on a time-division highway, each frame being of n bits duration and including one bit from each of n grunts stored in the array. A selected grunt is extracted from the highway by commencing a count of the bits on the highway with a first bit of the selected grunt and by extracting the first bit and every n.sup.th bit thereafter. Memory malfunction is indicated when the number of rows in the array containing parity errors exceeds a predetermined threshold number.
A data access circuit for storing a string of successive binary bits in a memory array, the memory array including a plurality of intersecting rows and columns, each row and each column intersection consisting of a binary storage cell, each storage cell storing one binary bit,
In a memory array comprising a plurality of intersecting rows and columns, each row and column including a plurality of binary storage cells, each storage cell storing one binary bit, means for checking the parity of the bits stored in each row of the memory array and means responsive to the checking means for indicating a malfunction in the memory array,
A method for storing a string of successive binary bits in a memory array, the memory array including a plurality of intersecting rows and columns, each row and column intersection consisting of a binary storage cell, each storage cell storing one binary bit, the method comprising the step of producing repetitive loading sequences, each loading sequence being associated with an individual column of the memory array, and each loading sequence further including the steps of,
A method for selectively extracting a multibit binary word from a memory array, the memory array containing n multibit binary words, the method comprising the steps of,
A method for detecting a malfunction in a memory array, the memory array consisting of a plurality of intersecting rows and columns, each row and column including a plurality of binary storage cells, each storage cell storing one binary bit, the method comprising the steps of,
A data access circuit, comprising, means for identifying selected multibit binary words to be extracted from a memory array containing n multibit binary words and means for extracting the selected multibit binary words from the memory array, the extracting means, including, means for reading out the n multibit binary words from the memory array, means responsive to the reading out means for distributing the bits of the multibit binary words to time slots in frames on a time-division highway, each frame being of n bits duration and including one bit from each of the n multibit binary words, characterized by the extracting means further including,
Dependencies are inferred from the claim text.