US 4,069,510 AGranted

Interrupt status register for interface adaptor chip

AssigneeMotorola, Inc.

InventorsEarl F. Carlow, Michael F. Wiles

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Abstract

A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA. A peripheral interface adaptor includes a plurality of data bus buffer circuits coupled to a bidirectional data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. A direction of data flow at the peripheral interface data bus is controlled by a data direction register. Data from the data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, the data direction register and a data register. Data from the peripheral data bus the data direction register and the control register are transferred via the output bus to the data bus buffers. Control circuits include an interrupt/status logic circuit for transmitting control signals to and receiving interrupt signals from a peripheral unit coupled to the interface circuit.

Claims6

Dependent claims

In an interface adaptor for interfacing between a peripheral data bus coupled to a peripheral device and to a system data bus coupled to processor means for executing a plurality of instructions, interrupt circuitry comprising:

an interrupt conductor for conducting an interrupt request signal from said peripheral device;
interrupt circuit means coupled to said interrupt conductor means for receiving said interrupt request signal and generating an interrupt request output signal in response to said interrupt request signal;
an interrupt output conductor coupled to said interrupt circuit means for conducting said interrupt request output signal;
first storage circuit means responsive to said interrupt circuit means and coupled between said interrupt circuit means and said system data bus for receiving and storing interrupt request status information representative of whether or not any interrupt request signal has been received by said interrupt circuit means;
a read conductor responsive to said processor means for conducting a read signal from said processor means to said interface adaptor;
address conductors responsive to said processor means for cnducting address signals representative of the location of said first storage circuit means form said processor means to said interface adaptor means;
address decoding means responsive to said address conductors for decoding said address signals to produce a selection signal;
and
means responsive to said selection signal and to said read signal and coupled to said first storage circuit means and to said system data bus for electrically coupling said first storage circuit means to said system data bus to effect reading said interrupt request status information by said processor means.

6 more elements

Dependencies are inferred from the claim text.