Inverter circuit arrangements
AssigneeFerranti Limited
InventorDavid Latham Grundy
Life of this patent
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Abstract
An inverter has a bipolar transistor and a field-effect transistor. The base gate electrodes are connected to the inverter input, and the collector and source electrodes are connected to the inverter output. The transistors are in series between supply rails. The lower of two possible input voltage levels causes the bipolar transistor to be switched OFF and the field-effect transistor to be switched ON, and the higher possible input voltage level causes the bipolar transistor to be switched ON and the field-effect transistor to be switched OFF. Base current level control is provided for discharging parasitic capacitance across the bipolar transistor when the latter is switched ON.
Claims12
An inverter circuit arrangement within a monolithic semiconductor body comprising a shallow epitaxial layer of one conductivity type on a substrate of the same conductivity type, the arrangement including at least a pair of circuit elements spaced from each other within the semiconductor body, each circuit element including a defined region of the epitaxial layer, a buried layer of opposite conductivity type at the interface between the defined region of the epitaxial layer and the substrate, a heavily doped isolation barrier of opposite conductivity type, said isolation barrier extending through the epitaxial layer into contact with the buried layer, and the defined region including a surface portion remote from the substrate, said surface portion having a part which is of said opposite conductivity type, one of said pair of circuit elements comprising a bipolar transistor with a collector comprising the combination of the buried layer and the isolation barrier, a base including an unmodified part of the defined region of the epitaxial layer, an emitter comprising the part of said opposite conductivity type of the surface portion of the defined region, the emitter being surrounded by material of said one conductivity type within the semiconductor body, and the bipolar transistor having electrode connections to the collector, the base and the emitter, the other circuit element comprising a field-effect transistor with a channel region including an unmodified part of the defined region of the epitaxial layer, the part of said opposite conductivity type of the surface portion of the defined region is contiguous with the isolation barrier, and bisects the remaining part of said one conductivity type of the surface portion into two regions, the part of said opposite conductivity type comprising the gate of the field-effect transistor, the remaining two regions of the surface portion comprising the source and the drain, and the field-effect transistor having electrode connections to the gate, the source and the drain, there also being provided within the circuit arrangement electrical connections such that the base of the bipolar transistor and the gate of the field-effect transistor are connected in common to receive input signals to the circuit arrangement, the collector of the bipolar transistor and the source of the field-effect transistor are connected in common to provide the output for the circuit arrangement, the drain of the field-effect transistor is connected to a point to be maintained at a first reference potential level, and the emitter of the bipolar transistor is connected to a point to be maintained at a second reference potential level, each input signal to the circuit arrangement to have two possible voltage levels, with one of the two possible input voltage levels causing the bipolar transistor to be switched ON and the field-effect transistor to be switched OFF, and the other of the two possible input voltage levels causing the bipolar transistor to be switched OFF and the field-effect transistor to be switched ON.
An inverter circuit arrangement within a monolithic semiconductor body comprising a shallow epitaxial layer of one conductivity type on a substrate of the same conductivity type, the arrangement including a plurality of inverters with each inverter comprising a pair of circuit elements spaced from each other within the semiconductor body, each circuit element including a defined region of the epitaxial layer, a buried layer of opposite conductivity type at the interface between the defined region of the epitaxial layer and the substrate, a heavily doped isolation barrier of opposite conductivity type, said isolation barrier extending through the epitaxial layer into contact with the buried layer, and the defined region including a surface portion remote from the substrate, said surface portion having a part which is of said opposite conductivity type, one of said pair of circuit elements comprising a bipolar transistor with a collector comprising the combination of the buried layer and the isolation barrier, a base including an unmodified part of the defined region of the epitaxial layer, an emitter comprising the part of said opposite conductivity type of the surface portion of the defined region, the emitter being surrounded by material of said one conductivity type within the semiconductor body, and the bipolar transistor having electrode connections to the collector, the base and the emitter, the other circuit element comprising a field-effect transistor with a channel region including an unmodified part of the defined region of the epitaxial layer, the part of said opposite conductivity type of the surface portion of the defined region is contiguous with the isolation barrier, and bisects the remaining part of said one conductivity type of the surface portion into two regions, the part of said opposite conductivity type comprising the gate of the field-effect transistor, the remaining two regions of the surface portion comprising the source and the drain, and the field-effect transistor having electrode connections to the gate, the source and the drain, there also being provided within the circuit arrangement electrical connections such that the base of the bipolar transistor and the gate of the field-effect transistor are connected in common to receive input signals to the circuit arrangement, the collector of the bipolar transistor and the source of the field-effect transistor are connected in common to provide the output for the circuit arrangement, the drain of the field-effect transistor is connected to a point to be maintained at a first reference potential level, and the emitter of the bipolar transistor is connected to a point to be maintained at a second reference potential level, each input signal to the circuit arrangement to have two possible voltage levels, with one of the two possible input voltage levels causing the bipolar transistor to be switched ON and the field-effect transistor to be switched OFF, and the other of the two possible input voltage levels causing the bipolar transistor to be switched OFF and the field-effect transistor to be switched ON.
Dependencies are inferred from the claim text.