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AssigneeThe United States of America as represented by the Administrator of the National Aeronautics and Space Administration
InventorAnthony J. Miller
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A binary coded input signal is converted to a binary coded decimal signal having N decades by employing N four bit shift registers. The bits of the input signal are sequentially supplied, in order, to the least significant position of the register for the units decade, with the most significant bit of the input signal being applied to the units register first. Each of the registers includes a right shift-parallel load mode control input terminal. In response to the sum of the values stored in each register and the binary value 0011 being less than the binary value 1000, the mode control input terminal is activated to shift the register contents one bit to the right. In response to the sum being greater than 1000, the mode control input terminal is activated to load the sum into the register. A binary one is loaded into the least significant bit position of the register for the adjacent higher decade in response to the sum being greater than 1000.
Apparatus for converting a binary coded input signal to a binary coded decimal output signal having N decades comprisng N shift registers each having four bit positions, means for sequentially supplying the bits of the input signal to the least significant bit position of the register for the units decade of the binary coded decimal signal, the bits of the input signal being supplied in order to the least significant bit position of the units decade register with the most significant bit of the input signal being applied first, each of said registers having a right shift-parallel load most control input means, and means responsive to the sum of the value stored in each of said registers and the binary value 0011 for:
Apparatus for converting a binary coded input signal to a binary coded decimal output signal having N decades comprising N shift registers each having four bit positions, means for sequentially supplying the bits of the input signal to the least significant bit position of the register for the units decade of the binary coded decimal signal, the bits of the input signal being supplied in order to the least significant bit position of the units decade register with the most significant bit of the input signal being applied first, each of said registers having a right shift-parallel load mode control input means, and means for:
Apparatus for converting a binary coded input signal to an output signal having a binary code of base K, wher K >
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