MOS Dynamic random access memory having an improved sensing circuit

In a memory circuit:

• bit line means having first and second portions over which electrical potentials representative of data to be stored in the memory are sensed and restored;
• memory cell means for storing the electrical potentials representative of data to be read out therefrom and restored thereto in use;
• switch means for electrically coupling the electrical potentials, representative of the stored and restored data, between said bit line means and said memory cell means in response to address signals applied to said switch means;
• sense amplifier means coupled between first and second portions of said bit line means for sensing the difference in electrical potential therebetween generated in response to electrical potential read from one of said addressed memory cell means onto one of said first and second portions of said bit line means;
• and
• buffer line amplifier means coupled between said sense amplifier means and said bit line means for isolating capacitance of said sense amplifier means from said bit lines means wherein said buffer line amplifier means includes, transistor means having a gate terminal and first and second other terminals, said gate terminal being connected to one of said bit line portions, and said other first and second terminals being connected for source follower amplifier operation relative to input signals received from said bit line means.