Associative memory

An associative memory designed to perform search and logical operations on attributive information presented in the form of multi-digit associative words which are sets of a given number of binary associative indications, comprising

• an input register to receive and store the code of the first operand, which is a given set of binary indications, having control outputs and
• flip-flops with an input, a direct output, and an inverse output,
• the number of said flip-flops of said input register being equal to the number of binary indications in said code of the first operand,
• said flip-flops of said input register being divided into groups;
• an interrogation register to receive and store the interrogation code in the form of a given set of binary indications made up of
• flip-flops with direct and inverse inputs, and direct and inverse outputs,
• the number of said flip-flops of said interrogation register being equal to the number of said flip-flops of said input register,
• said flip-flops of said interrogation register being divided into groups equal in number to said groups of said flip-flops of said input register;
• coincidence circuits which have first and second inputs and outputs,
• said coincidence circuits being arranged in groups, two of said coincidence circuits being in each group,
• the number of said coincidence circuits being equal to the number of said flip-flops of said input register,
• said first inputs of first and second coincidence dircuits in each said group being connected, respectively, to said direct and inverse outputs of said respective flip-flops of said input register,
• said outputs of said first and second coincidence circuits in each said group being connected, respectively, to said direct and inverse inputs of said respective flip-flop of said interrogation register;
• interrogation decoders for converting said interrogation code which have inputs and outputs;
• Or circuits which have first and second inputs and outputs,
• said OR circuits being arranged in groups, two OR circuits being in each group,
• the number of said OR circuits being equal to the number of said flip-flops of said input register,
• said first inputs of first and second OR circuits of each said group being connected, respectively, to said direct and inverse outputs of said respective flip-flop of said interrogation register,
• said outputs of said first and second OR circuits of each said group being connected to respective inputs of said interrogation decoders;
• a mask register to receive and store the mask code in the form of a given set of binary indications, which show said indications of said interrogation code irrelevant to the search operation to be performed, with
• flip-flops having inputs and direct outputs,
• the number of said flip-flops of said mask register being equal to the number of said flip-flops of said input register,
• said flip-flops of said mask register making up ring shift registers in a number equal to said groups of said flip-flops in said input register,
• said direct outputs of said flip-flops of said mask register being connected to said second inputs of said OR circuits of said respective group;
• an operation decoder to control information transfer from said outputs of said flip-flops in said input register to said inputs of said respective flip-flops in said interrogation register in a direct code and inverse code, depending on the logical operation to be performed, having inputs and outputs,
• first and second outputs of said operation decoder being connected to said second inputs of, respectively, said first and second coincidence circuit in each said group of said coincidence circuits;
• and
• a data storage unit to perform arithmetic and parallel logical operations on attributive information having interrogation buses and control inputs,
• said interrogation buses of said data storage unit being connected to said outputs of said respective interrogation decoders,
• said control inputs of said data storage unit being connected to respective outputs of said operation decoder.