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US 4,069,429 AGranted
IGFET clock generator
AssigneeHarris Corporation
InventorsWilliam H. White, Mario A. Lorie
Life of this patent
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Abstract
A circuit having an input terminal connected to one input of a NOR gate through three cascaded IGFET inverters and connected directly to the other input of the NOR gate for producing an output pulse in response to an input signal going from a first voltage level to a second voltage level. The output pulse has a width which is a function of the time delay imparted by the high resistance device of two unbalanced IGFET inverters and the parasitic capacitors at the output of each of the unbalanced inverters.
Claims17
A pulse producing circuit comprising:
- input means;
- output means having a first input connected to said input means and a second input;
- three inverter means connected in cascade between said input means and said second input of said output means, two of said inverter means being unbalanced in their response to voltage level changes at said input means each for producing a time delay;
- said output means produces a pulse for a specific direction of voltage level change at said input means for a duration determined by said time delays.
1 more element
A circuit comprising:
- an input terminal;
- three inverter means connected in cascade with said input terminal, two of said inverter means responding slower to a signal at said input terminal of a first voltage level than a second voltage level;
- and
- output means, having a first input from said input terminal and a second input from the output of the third inverter means, for producing an output pulse in response to an input signal at said input terminal of said first voltage level and whose duration is a function of a slower response of said two of said inverter means.
1 more element
Dependencies are inferred from the claim text.