Transistor-transistor-logic circuit

An improved monolithically integrated transistor-transistor-logic circuit comprising:

• an input transistor having a collector region, a base region, and at least one emitter region connected to an input;
• an output transistor having a collector region, a base region, and at least one emitter region;
• an electrical path coupling the base region of said output transistor to the collector region of said input transistor;
• a first source of potential electrically coupled by means of a first impedance to the base region of said input transistor and by means of a second impedance to the collector region of said output transistor;
• a second source of potential electrically coupled to the emitter region of said output transistor;
• and
• circuit means electrically coupled to said base region of said output transistor for biasing said output transistor into a first binary state when said input transistor malfunctions by failing to provide a current path for biasing said output transistor into a second binary state;
• said input transistor and said output transistor being NPN transistors;
• said first source of potential having a more positive value than said second source of potential;
• and
• said input transistor having a plurality of emitter regions;
• said improved circuit providing a NAND logical output function at the collector of said output transistor.

An improved monolithically integrated transistor-transistor-logic circuit wherein the integrated form of said circuit, in part, comprises:

• a semiconductor body having a substrate doped with impurities of a first conductivity type;
• an input transistor having a collector region, a base region, and at least one emitter region connected to an input;
• an output transistor having a collector region, a base region, and at least one emitter region;
• an electrical path coupling the base region of said output transistor to the collector region of said input transistor;
• a first source of potential electrically coupled by means of a first impedance to the base region of said input transistor and by means of a second impedance to the collector region of said output transistor;
• a second source of potential electrically coupled to the emitter region of said output transistor;
• and
• circuit means electrically coupled to said base region of said output transistor for biasing said output transistor into a first binary state when said input transistor malfunctions by failing to provide a current path for biasing said output transistor into a second binary state;
• a first semiconductor region doped with impurities of a second conductivity type buried within said body and forming a subcollector for said input transistor;
• a second semiconductor region doped with impurities of said first conductivity type disposed over said first semiconductor region, and forming a base region for said input transistor;
• at least one third semiconductor region doped with impurities of said second conductivity type disposed in said second semiconductor region at its upper surface forming at least one emitter region for said input transistor;
• a fourth semiconductor region contiguous with said first semiconductor region and doped with impurities of said second conductivity type having a doping concentration less than the doping concentration of said first semiconductor region, thereby providing a semiconductor region of higher resistivity than the resistivity of said first semiconductor region;
• and
• said fourth semiconductor region having an electrical connection to said first source of potential.