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US 4,068,303 AGranted
Address translation managing system with translation pair purging
AssigneeHitachi, Ltd.
InventorHiroshi Morita
Life of this patent
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Abstract
In a data processing system employing a virtual storage system, a plurality of address translation pairs each consisting of a logical address in a virtual storage space and a real address in a real storage space, are registered in a buffer storage device to swiftly translate a logical address into the corresponding real address. According to this invention, in the case of purging a virtual space out of multiple virtual spaces only the address translation pairs corresponding to the virtual space are purged so that the processing performance of the data processing system can be improved.
Claims9
An address translation system in which a real space is shared by a plurality of logical spaces, comprising:
- a table base stack having a plurality of storage units, each storage unit storing a base address characteristic of a different virtual space, and each of said storage units having an identification flag characteristic thereof;
- a translation lookaside buffer for registering address translation pairs each consisting of a virtual address and a real address, which buffer has with respect to said translation pairs the identification parts in which the identification flags characteristic of said storage units of said table base stack are set;
- an output means for searching said storage units of said table base stack by using as a key a base address of a virtual space to be invalidated when an instruction is issued for invalidating an address translation pair in said translation lookaside buffer and for delivering the identification flag of the storage unit in which the desired base address is stored;
- a comparison means for sequentially reading said identification flags out of said identification parts of said translation lookaside buffer and comparing the read-out flags with signals from said output means;
- and
- means for purging the address translation pair corresponding to the identification part when the identification flag thereof produces a coincidence in the comparison performed by said comparison means.
3 more elements
An address translation system in which a real space is shared by a plurality of logical spaces, comprising:
- a plurality of registers, each having a number characteristic thereof and each storing a base address of a different virtual space;
- a translation lookaside buffer for registering address translation pairs each consisting of a virtual address and a real address, which buffer has with respect to said translation pairs the identification parts in which the numbers characteristic of said registers are set;
- a first comparison means for comparing an address data represented by an operand address of an instruction with the base addresses read sequentially out of said registers, when the instruction is issued for invalidating an address translation pair in said translation lookaside buffer;
- an output means for delivering the number characteristic of the register which contributes to a coincidence in the comparison performed by said first comparison means;
- a second comparison means for comparing a signal from said output means with signals read sequentially out of the identification parts of said translation lookaside buffer;
- and
- means for purging only an address translation pair corresponding to the identification part which contributes to a coincidence in the comparison performed by said second comparison means.
4 more elements
An address translation system having a real spaced shared by plural logical spaces and employing multiprocessor system in which plural processors share a single main memory, comprising:
- a plurality of registers provided in each of said processors for storing the base addresses of different virtual spaces;
- a translation lookaside buffer provided in each of said processors for registering address translation pairs each consisting of a virtual address and a real address, which buffer has with respect to said translation pairs the identification parts in which the numbers characteristic of said registers are set;
- a first comparison means provided in each of said processors for comparing the address data represented by an operand address of an instruction with the base addresses read sequentially out of said registers;
- an output means provided in each of said processors for delivering the number of the register which contributes to a coincidence in the comparison performed by said first comparison means;
- a second comparison means provided in each of said processors for comparing a signal from said output means with signals read sequentially out of the identification parts of said translation lookaside buffer;
- means provided in each of said processors for purging only an address translation pair corresponding to the identification part which contributes to a coincidence in the comparison performed by said second comparison means;
- means for sending a purging instruction to the other processors when an address translation pair is purged from a translation lookaside buffer of one processor;
- means for applying to said first comparison means of said one processor an address data represented by an operand address of an instruction used in said one processor;
- means for storing said address data in a specified address in said main memory;
- and
- means for reading said address data out of said specified address of said main memory by said other processors and for applying the read address data to said first comparison means.
8 more elements
Dependencies are inferred from the claim text.