Circuit for detecting a missed commutation in an inverter

A circuit for detecting a missed commutation in a self-commutating inverter including a series combination of at least first and second gate controlled rectifiers and a commutating interval current limiting center tapped reactor connected in series with and interposed between said rectifiers, and commutating means connected to the center tap of said reactor, said series combination being connected across a direct current source of potential, comprising:

• a. means coupled to the center tap of said reactor for generating a first signal upon detecting and for the duration of an interval when both of said rectifiers are ON;
• b. means, responsive to a first pulse used to initiate the interval when either of said first and second recitifiers is to be ON, for generating a second signal the duration of which is longer than the time necessary to ensure that both of said rectifiers would normally have turned ON but shorter than the final time when both of said rectifiers would still have remained ON;
• and
• c. means responsive to said first and second signals for generating a control signal to cause cessation in the operating of said inverter if said first signal fails to occur during the total occurrence of said second signal.