US 4,068,229 AGranted

High speed coding system for PCM signals with coarse and fine coding in an overlapping range

AssigneeFujitsu Limited

InventorsYukihiko Minejima, Masahiro Yamashita, Haruo Tsuda

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Abstract

A high speed coding system utilizes first and second coders. Specified input bits supplied from a sample and hold circuit are first coded by the first coder during a first coding stage and are in turn coded again by the second coder during a second coding stage. The coding results of the first coder govern the generation of the initial reference voltage of the first bit for coding in the second coder in order to provide an assumption that the necessary number of bits of the first coder are already coded by the second coder. There is an overlapping coding range of the first and second coders, and the system assures that coding errors in the first coder may be corrected within the overlapping coding range through coding of the coding bits of the first coder within the overlapping coding range of the second coder.

Claims6

Dependent claims

A high speed coding system for coding an input signal into a PCM signal during first and second coding stages, said coding system comprising

input means for supplying an input signal to be coded;
sample and hold means connected to the input means for sampling and holding the input signal;
first coding means for coding bits from a most significant bit to an m.sup.th bit corresponding to the sampled and held input signal of the sample and hold means during the first coding stage, the first coding means having an output;
analog memory means connected to the sample and hold means for holding the sampled and held input signal during the second coding stage;
second coding means having a feedback loop including a decoder, said decoder providing an initial reference voltage corresponding to the output of the first coding means for the first bit to be coded of the second coding stage for coding bits from an m'.sup.th bit to a least significant bit corresponding to the held signal of the analog memory means during the second coding stage, m' being equal to or less than m magnitude, the second coding means having an output;
combining means connected to the outputs of the first and second coding means for adding the coded signals produced by the first coding means to the coded signals produced by the second coding means to provide a digital output signal representative of the sampled and held input signal;
and
output means connected to the combining means for providing the digital output signal of the combining means in series.

5 more elements

A high speed coding system for PCM signals, comprising

input means for supplying a signal to be coded;
an analog memory having an input coupled to the input means and an output;
first coding means connected to the input means for coding bits from a most significant bit to an m.sup.th bit corresponding to the signal to be coded during a first coding stage, the first coding means comprising a comparator having a first input coupled to the input means, a second input and an output connected to the combining means, a memory having an input connected to the output of the comparator and outputs, said memory having a predetermined number of flip flops, and a decoder having inputs connected to outputs of the memory and an output connected to the second input of the comparator, the first coding means having an output;
second coding means connected to the first coding means and supplied with coded signals produced by the first coding means for providing an initial reference voltage for a second coding stage and for coding bits from an m'.sup.th bit to at least significant bit corresponding to the signal to be coded during the second coding stage, m' being equal to or less than m in magnitude, the second coding means comprising a comparator having a first input connected to the output of the analog memory, a second input and an output connected to the combining means, a memory having inputs connected to the outputs of the memory of the first coding means, an input connected to the output of the comparator of the second coding means and outputs, the memory of the second coding means comprising a number of flip flops greater than the predetermined number, and a decoder having inputs connected to the outputs of the memory and an output connected to the second input of the comparator, the second coding means having an output;
a first shift register having an input connected to the output of the comparator of the first coding means and outputs and a second shift register having an input connected to the output of the second coding means and outputs;
combining means connected to the outputs of the first and second coding means for adding the coded signals produced by the first coding means to the coded signals produced by the second coding means to provide a digital output signal;
and
output means connected to the combining means for providing the digital output signal of the combining means in series.

5 more elements

A high speed coding system for PCM signals, comprising

input means for supplying a signal to be coded;
an analog memory having an input coupled to the input means and an output;
first coding means connected to the input means for coding bits from a most significant bit to an m.sup.th bit corresponding to the signal to be coded during a first coding stage, the first coding means comprising a comparator having a first input coupled to the input means, a second input and an output connected to the combining means, a memory having an input connected to the output of the comparator and outputs, said memory having a predetermined number of flip flops, and a decoder having inputs connected to outputs of the memory and an output connected to the second input of the comparator, the first coding means having an output;
second coding means connected to the first coding means and supplied with coded signals produced by the first coding means for providing an initial reference voltage for a second coding stage and for coding bits from an m'.sup.th bit to a least significant bit corresponding to the signal to be coded during the second coding stage, m' being equal to or less than m in magnitude, the second coding means comprising a comparator having a first input connected to the output of the analog memory, a second input and an output connected to the combining means, a memory having inputs connected to the outputs of the memory of the first coding means, an input connected to the output of the comparator of the second coding means and outputs, the memory of the second coding means comprising a number of flip flops greater than the predetermined number, and a decoder having inputs connected to the outputs of the memory and an output connected to the second input of the comparator, the second coding means having an output;
a first shift register having an input connected to the output of the comparator of the first coding means and outputs and a second shift register having an input connected to the output of the second coding means and outputs;
combining means connected to the outputs of the first and second coding means for combining the coded signals produced by the first and second coding means and compensating for coding errors occurring in an overlapping coding range of the first and second coding means, said combining means comprising a plurality of flip flops having inputs and outputs and a plurality of gate means connected between the outputs of the first and second shift registers and the inputs of the flip flops;
and
output means connected to the combining means for providing the combined coded signals, said output means including a parallel to series converter comprising a third shift register having a plurality of inputs connected to the outputs of the flip flops and an output providing series PCM signals.

5 more elements

Dependencies are inferred from the claim text.