Phase locked loop circuit
AssigneeHitachi, Ltd.
InventorTakao Yokoyama
Life of this patent
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AssigneeHitachi, Ltd.
InventorTakao Yokoyama
Estimating the term…
Phase locked loop (PLL) circuit comprises, a phase detector including first and second cascade-connected differential pairs of transistors constituting an analog multiplier with each one of the differential pair transistors supplied with two inputs, a low pass filter for converting the detection output into a D.C. control voltage, and an emitter-coupled multivibrator including constant current sources for determining the oscillation frequency with a timing capacitor. The PLL circuit is provided with constant current adjusting means for variably setting or determining the current through a constant current source connected to the second differential pair of transistors and the currents through the current sources determining the oscillation frequency in a correlated manner through a common variable resistor. Thereby, dispersions in the loop gain of the PLL circuit are reduced.
A phase locked loop circuit comprising a phase detector including an analog multiplier formed of a transistor differential amplifier for detecting the phase difference of two input signals through a constant current source connected to said differential amplifier, a low pass filter for integrating the phase difference output of said phase detector and converting it into a D.C. voltage, and a voltage-controlled oscillator generating an oscillation frequency determined by the capacitance of a timing capacitor and currents flowing through constant current sources connected respectively to both ends of said timing capacitor and controlled by said D.C. voltage output of said low pass filter and feeding back the oscillation output as one of said two input signals, said phase locked loop circuit comprising:
A phase locked loop circuit comprising a phase detector circuit, a low pass filter circuit and a voltage-controlled oscillator circuit, said phase detector circuit supplying a detection output signal proportional to the phase difference of the input signal and the oscillation output signal of said voltage-controlled oscillator circuit to said low pass filter, the phase of the oscillation output signal of said voltage-controlled oscillator circuit being controlled by the output signal of said low pass filter circuit, in which:
An integrated circuit for a phase locked loop circuit formed in a monolithic semiconductor chip comprising:
Dependencies are inferred from the claim text.