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US 4,068,174 AGranted
Digital carrier wave detect circuitry
AssigneeInternational Business Machines Corporation
InventorLawrence Eugene Svelund
Life of this patent
Estimating the term…
Abstract
Readily available digital logical circuit components are arranged in circuitry for enhancing demodulation of frequency shifted or phase shifted modulation signals in the presence of a received carrier wave and inhibiting demodulation in the absence of any recognized carrier wave. The circuitry is arranged for measuring the time between adjacent impulses as received including noise impulses which penetrate an input band-pass filter. The preponderance of signal impulses lie within predeterminable limits, however, and the circuitry is arranged for indicating the presence of a data signal despite some noise impulses passing through the filter. The electronic circuit components are conventional and also are readily laid down in semi-conductor structures of the popular types.
Claims15
Digital carrier wave detect circuitry for digital data communications receiving circuitry, comprising
- input terminals at which at least the train of transitions of a digital data modulated carrier wave signal is applied,
- output terminals at which a signal level indicative of said carrier wave detected is presented,
- inputting terminals at which a clock pulse train is applied having a number of impulses greater than the number of said transitions of said wave for a given period of time,
- a counting circuit having reset, input and output terminals,
- And gating circuitry connected to said output terminals of said counting circuit and having output terminals at which electric levels are delivered for a plurality of predetermined counts corresponding to the appearance of said transitions in said modulated wave with respect to said impulses of said clock pulse train,
- control circuitry connected to said input terminals, to said inputting terminals and to said reset and input terminals of said counting circuit for gating said clock impulses to said counting circuit for counting clock impulses between transitions of said modulated wave, and
- output circuitry coupled between said AND gating circuitry output terminals and said signal level output terminals and responsive to a predetermined count for indicating properly spaced transitions.
4 more elements
Digital carrier wave detect circuitry for digital data communications receiving circuitry, comprising
- input terminals at which a digital data modulated carrier wave signal is applied,
- output terminals at which a signal level indicative of carrier detected is presented,
- a delay circuit connected to said input terminals,
- an exclusive OR (XOR) gating circuit connected to said input terminals and to said delay circuit and having an output terminal at which transitions and noise pulses passing said input terminals and reappearing at the output of said XOR gating circuit appear,
- a latching flip-flop circuit having a set terminal connected to the output terminal of said XOR gating circuit, a reset terminal, and at least one output terminal,
- a number of concatenated flip-flop stages each having data, clock, and complementary output terminals, with the data terminal of the first stage connected to said one output terminal of said latching flip-flop circuit, with the erect output terminal of the first stage connected to the reset terminal of said latching flip-flop circuit, and with the erect terminal of each stage save the last stage connected to the data terminal of the succeeding stages,
- a set of complementary timing wave inputting terminals at which a source of complementary timing waves is applied with the terminals for the primary timing wave connected in common to the clock terminals of said concatenated flip-flop stages,
- a forward counter circuit having count input, reset and output terminals,
- four AND gating circuits having output terminals and having a multiple of input terminals permutated among said output terminals of said counter circuit for delivering output levels individual to said AND gating circuits and indicative of the maximum and minimum counts of two predetermined ranges of counts corresponding to said digital data conveyed by said signal,
- another latching flip-flop circuit having set, reset and complementary output terminals with one set of output terminals coupled to said carrier detect output terminals,
- an OR gating circuit connected to said set terminals of said latching flip-flop circuit and having input terminals individually connected to the output terminals of said AND gating circuits indicative of said predetermined minimum counts,
- another OR gating circuit connected to said reset terminals of said latching flip-flop circuit and having input terminals individually coupled to the output terminals of the other of said AND gating circuits,
- a counter input AND gating circuit having an output lead connected to the input terminals of said counter circuit and having at least three input leads with an inverting input circuit in one of said leads,
- a connection from the output terminal of the one AND gating circuit indicative of the greater of said maximum predetermined counts to said inverting input circuit, and
- another AND gating circuit having one input lead connected to the complementary timing wave inputting terminals for the secondary wave, another input connected to the output terminal of the last flip-flop stage of said concatenated flip-flop stages and an output lead connected to another input lead of said counter input AND gating circuit.
12 more elements
Digital carrier wave detect circuitry for digital data communications receiving circuitry, comprising
- input terminals at which at least the train of transitions of a digital data modulated carrier wave signal is applied,
- output terminals at which a signal level indicative of said carrier wave detected is presented,
- inputting terminals at which a clock pulse train is applied having a number of impulses greater than the number of said transitions of said wave for a given period of time,
- a counting circuit having reset, input and output terminals,
- comparing circuitry connected to said output terminals of said counting circuit and having output terminals at which electric levels are delivered for a plurality of predetermined counts corresponding to the appearance of said transitions in said modulated wave with respect to said impulses of said clock pulse train,
- control circuitry connected to said input terminals, to said inputting terminals and to said reset and input terminals of said counting circuit for gating said clock inpulses to said counting circuit for counting clock impulses between transitions of said modulated wave, and
- output circuitry coupled between said comparing circuitry output terminals and said signal level output terminals and responsive to a predetermined count for indicating properly spaced transitions.
4 more elements
Dependencies are inferred from the claim text.