Binary frequency divider

In a binary frequency divider stage circuit with complementary insulated gate field effect transistors (MOST) powered by a constant voltage source, comprising an input for introducing an input signal and at least three logical nodes, at least one output (A) connected to one of said three nodes, each logical node being an interconnection between the drains of at least one n-channel MOST and at last one p-channel MOST, each logical node being connected to at least one of said p- and n-channel MOST of at least one other node the source of one of the p- and n-channel MOST (1) of at least one of the nodes being connected to one terminal of the voltage source and the source of the p- and n-channel MOST (4) of the same node being connected to the drain of a third MOST (2), the source of which is connected to the other terminal of the voltage source, said p- and n-channel MOST and said third MOST of said one node arranged such that said one node is controlled by two variables, one being the input signal (I) and the other being the signal from another logical node (E), in such a way that one variable drives the gate(s) of the third MOST and the gate of the one of said p- and n-channel MOST having a channel type opposed to that of said third MOST and the other variable drives the gate of the other p- and n-channel MOST, allowing the corresponding node to float when said p-channel MOST as well as said n-channel MOST of said one node are both blocked, the improvement comprising means for connecting each node, for one only of the two logical states of said input, by at least one conducting MOST, to either terminal of said constant voltage source, whereby said nodes do not float for said one logical state of said input.