Frequency number controlled clocks

In a system utilizing frequency modulated clock signals generated by voltage controlled oscillators, the instantaneous frequency of the generated clock signals being proportional to analog control voltages, the improvement comprising;

• memory means for storing frequency data words,
• an oscillator means comprising a plurality of voltage controlled oscillators wherein the frequencies of such oscillators are responsive to analog frequency control voltages,
• assignment means wherein control signals are generated whereby said analog frequency control voltages are assigned to members of said plurality of voltage controlled oscillators,
• addressing means responsive to said assignment means whereby said frequency data words are read out from said memory means,
• conversion means wherein said frequency data words read out from said memory means are converted to said analog frequency control voltages,
• signal selection means responsive to said assignment means whereby said analog frequency control voltages are selectively directed to members of said plurality of voltage controlled oscillators, and
• signal adding means wherein analog voltages are added to said analog frequency control voltages thereby generating frequency modulation.

In a system utilizing clock signals generated by voltage controlled oscillators, the frequency of the generated clock signals being proportional to analog control voltages, the improvement comprising;

• memory means for storing frequency data words and a tuning frequency data word,
• a plurality of voltage controlled oscillators wherein frequencies of such oscillators are responsive to said analog frequency control voltages,
• assignment means wherein control signals are generated whereby said analog frequency control voltages are assigned to members of said plurality of voltage controlled oscillators,
• addressing means responsive to said assignment means whereby said frequency data words are read out from said memory means and whereby said tuning frequency data word is caused to be read out from said memory means,
• a plurality of clock generating means, each member of which is associated with a corresponding member of said plurality of voltage controlled oscillators, wherein in response to frequency signals F.sub.O created by members of plurality of voltage controlled oscillators clock signals are generated at a frequency DF.sub.O, where D is a scale factor,
• a reference clock generator wherein a reference clock signal is created at a frequency F.sub.R,
• a signal select gate responsive to tuning select control signals wherein a selection is made from plurality of clock signals generated by said plurality of clock generating means,
• comparator means wherein said clock signal selected by said signal select gate is compared with said reference clock signal and wherein an error signal is created when said compared signals differ,
• a plurality of analog error memories, each member of which is associated with a corresponding member of said plurality of voltage controlled oscillators, and wherein selection of a member of said plurality of analog error memories is responsive to said tuning select control signals,
• tuning timing means wherein said tuning select control signals and tuning select read out signals are created repetitively for said plurality of voltage controlled oscillators and wherein tuning select control signals and tuning select read out signals are not created for corresponding members of plurality of voltage controlled oscillators that are in their assigned states, and
• conversion means wherein said frequency data words read out from said memory means are converted to said analog frequency control voltages;
• and further comprising a plurality of second error memory selection gates wherein said error signals stored in said plurality of analog error memories are read out responsive to said tuning select read out signals, a plurality of reference voltage controlled oscillators, voltage adding means whereby error signals caused to be read out of members of said analog error memories are added with corresponding members of said reference voltages.