US 4,066,874 A · Digital speed control system

Abstract

A digital speed control system includes a first binary up-counter called an Actual Count Register. The Actual Count Register is initially reset to contain all "0"'s. During a sample time, an input is applied to the Actual Count Register so that it counts up to a first binary number during the sample time. The first binary number represents a reference speed. The system includes a Reference Count Register. In response to read and store command, the first binary number is loaded into the Reference Count Register, where it remains until the next request for a new reference speed. The system further includes a first binary presettable up-counter called the Error Register. The Error Register counts up at the same rate and in response to the same count signal as the Actual Count Register. During a Transfer signal which follows the Read signal, the complement of the first binary number is transferred from the Reference Count Register into the Error Register. The system also includes a second binary presettable up-counter called an Acceleration Register. The inputs of the Acceleration Register are coupled to the outputs of the Actual Count Register so that during the transfer signal the complement of the first binary number is loaded into the Acceleration Register. A decoder connected to the outputs of the Error Register interprets its contents, and a second decoder interprets the contents of the the Acceleration Register.

Claims5

Dependent claims

A digital system for use in a system for controlling vehicular speed and acceleration, said digital system comprising:

counting signal means for generating a first counting signal representative of a first velocity, a second counting signal representative of a predetermined acceleration, and a third counting signal representative of a second velocity;
first counting means responsive to said first, second, and third counting signals and coupled to said counting signal means for counting from an initial value to a first binary number representative of said first velocity in response to said first counting signal, counting from said first binary number to a second binary number in response to said second counting signal, and counting from an initial value to a third binary number representative of said second velocity in response to said third counting signal;
second counting means coupled to said counting signal means and to said first counting means for storing the logical complement of said second binary number and counting from said complement to a fourth binary number in response to said third counting signal;
first means coupled to said first counting means and said second counting means for generating said complement, and entering said complement into said second counting means;
decoding means coupled to said second counting means for decoding said fourth binary number to produce a binary number representing the algebraic difference between said second binary number and said third binary number.

2 more elements

Dependencies are inferred from the claim text.

Digital speed control system

Life of this patent

Digital speed control system

Life of this patent

Abstract

Claims5