Method of manufacture of a gold diffused thyristor

#This invention relates to thyristors and, more particularly to gold doped fast turnoff thyristors.

#Since their introduction, thyristors have become more popular as circuit designers have continued to employ them in new and different ways. As new applications for thyristors are developed, greater emphasis is placed on improving the performance of the devices under demanding conditions of operation. Different applications require that the emphasis be placed on different characteristics of the device. For example, some potential applications will become commerically feasible only if the cost of the thyristors can be reduced. Other applications require that the devices be able to withstand higher reverse voltages or that they switch from a conductive to a nonconductive state more rapidly. Thus, the device designer is faced with a multifaceted problem.

#One of the principal concerns of the device designer is the interrelationship among the various device characteristics. For example, it is known that if gold is diffused into the interior of a thyristor, the minority carrier lifetime is decreased and thus turnoff time is reduced. However, the effect of the gold diffusion step on the cost of the device must be considered. Further, heavy blanket gold doping increases thyristor leakage current. Yet, in an effort to simplify and reduce the number of manufacturing steps, gold diffused thyristors have generally been manufactured with a blanket gold diffusion process. Consequently, excessive leakage current is sometimes a problem in gold diffused thyristors. Processes for localized gold diffusion have been developed. See, for example, U.S. Patent Application Ser. No. 405,489, filed on Oct. 11, 1973, in the name of Richard W. Kennedy, et al, and assigned to the assignee of the present invention, now U.S. Pat. No. 3,941,625. However, these processes frequently necessitated the addition of several manufacturing steps so that, while thyristors with good electrical characteristics were provided, cost sometimes became a problem.

#These and other features and objects of the present invention will become more apparent upon a perusal of the following description taken in conjunction with the accompanying drawings in which:

#FIG. 1 is an elevation view of a silicon wafer such as is utilized in the practice of the subject invention;

#FIGS. 2 and 3 show intermediate processing stages encountered when practicing the subject invention;

#Referring first to FIG. 1 there is shown a silicon wafer 21 defining two substantially parallel major surfaces 22 and 23. The wafer 21 is doped with a selected impurity such that it exhibits a selected conductivity type. For example, assume that the wafer 21 is doped with phosphorus to be of N-type conductivity. Selection of wafer thickness is within the ability of those skilled in the art and will depend on specific processes to be employed, voltage desired, etc., but will generally be in the range of 8-12 mils.

#Referring now to FIG. 2, the next processing step is illustrated. A dopant is diffused from each of the major surfaces 22 and 23 to form layers 24 and 25 of the opposite, in this example P, type conductivity. The dopant can be boron, gallium or aluminum and a proper depth will be reached in approximately 30 hours at about 1250.degree. C. A layer 26 of N-type conductivity remains in the center of the wafer 21.

#Referring next to FIG. 3, the subsequent processing step is illustrated. A mask 27, such as an oxide mask, is applied on the major surface 22. A second mask or layer of oxide 28 is also applied or grown on the major surface 23. An opening 29 is defined by the mask 27. The opening 29 is depicted in FIG. 3 as the right two-thirds of the surface 22 and it will be referred to as a cathode emitter opening 29 inasmuch as it exposes the region of the surface 22 that will be adjacent the cathode emitter layer of the SCR to be made.